CN-122028500-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Abstract

A semiconductor device includes a merging unit including first and second active patterns extending in a first direction and including first p-type transistors on the first active pattern and first n-type transistors on the second active pattern, a first half unit adjacent to the merging unit in a second direction and including a third active pattern, a second half unit adjacent to the merging unit in the second direction and including a fourth active pattern, and a logic circuit element on at least one of the third active pattern and the fourth active pattern. The first half unit and the second half unit each have a second unit height smaller than the first unit height of the merging unit. Each of the third and fourth active patterns has a second width smaller than the first width of each of the first and second active patterns.

Inventors

• CUI XIUBIN
• JIN BINGCHENG
• Pu Shenggao
• PU ZHI
• Pu Panji

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250801

Priority Date

20241112

Claims (20)

1. 1. A semiconductor device, comprising: A merging unit including a first active pattern and a second active pattern extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the merging unit further including a first p-type transistor on the first active pattern and a first n-type transistor on the second active pattern; a first half unit adjacent to the first active pattern of the merging unit in the second direction and including a third active pattern extending in the first direction; a second half unit adjacent to the second active pattern of the merging unit in the second direction and including a fourth active pattern extending in the first direction, and A logic circuit element on at least one of the third active pattern and the fourth active pattern, Wherein the merging unit has a first unit height in the second direction, and the first half unit and the second half unit each have a second unit height smaller than the first unit height in the second direction, and Wherein each of the first and second active patterns has a first width in the second direction, and each of the third and fourth active patterns has a second width smaller than the first width in the second direction.
2. 2. The semiconductor device of claim 1, wherein the first cell height is four times the second cell height.
3. 3. The semiconductor device of claim 1, wherein the first width is greater than twice the second width.
4. 4. The semiconductor device of claim 1, wherein the first p-type transistor includes a first channel pattern and a first p-type source/drain pattern, the first channel pattern being spaced apart and stacked from each other on the first active pattern in a third direction intersecting the first direction and the second direction, the first p-type source/drain pattern being located on the first active pattern and electrically connected to opposite sides of the first channel pattern in the first direction, respectively, Wherein the first n-type transistor includes a second channel pattern spaced apart from and stacked on the second active pattern in the third direction and a first n-type source/drain pattern on the second active pattern and electrically connected to opposite sides of the second channel pattern in the first direction, respectively, and Wherein the merging unit further includes a first gate line extending across the first and second active patterns in the second direction and at least partially surrounding each of the first and second channel patterns.
5. 5. The semiconductor device according to claim 4, wherein the logic circuit element includes at least one of a second n-type transistor on the third active pattern and a second p-type transistor on the fourth active pattern.
6. 6. The semiconductor device of claim 5, wherein the logic circuit element comprises the second n-type transistor on the third active pattern, Wherein the second n-type transistor includes a third channel pattern stacked in the third direction and spaced apart from each other on the third active pattern, a second n-type source/drain pattern on the third active pattern and respectively electrically connected to opposite sides of the third channel pattern in the first direction, and a second gate line extending across the third active pattern and at least partially surrounding each of the third channel patterns, and Wherein the semiconductor device further includes a first gate isolation pattern separating the first gate line from the second gate line between the combining unit and the first half unit.
7. 7. The semiconductor device of claim 5, wherein the logic circuit element comprises the second p-type transistor on the fourth active pattern, Wherein the second p-type transistor includes a fourth channel pattern stacked in the third direction and spaced apart from each other on the fourth active pattern, a second p-type source/drain pattern on the fourth active pattern and respectively electrically connected to opposite sides of the fourth channel pattern in the first direction, and a third gate line extending across the fourth active pattern and at least partially surrounding each of the fourth channel patterns, and Wherein the semiconductor device further includes a second gate isolation pattern separating the first gate line from the third gate line between the combining unit and the second half unit.
8. 8. The semiconductor device of claim 1, wherein the logic circuit element comprises a second n-type transistor on the third active pattern and a second p-type transistor on the fourth active pattern.
9. 9. The semiconductor device of claim 8, further comprising an interconnect line electrically connecting the second n-type transistor to the second p-type transistor and extending in the second direction.
10. 10. The semiconductor device according to claim 1, wherein the logic circuit element includes a capacitor on at least one of the third active pattern and the fourth active pattern.
11. 11. The semiconductor device according to claim 1, wherein the merging unit has a width in the first direction that is equal to a width of each of the first half unit and the second half unit in the first direction.
12. 12. The semiconductor device according to claim 1, wherein at least one of the first half unit and the second half unit has a width in the first direction different from a width of the merging unit in the first direction.
13. 13. The semiconductor device of claim 1, wherein at least one of the first half cell and the second half cell comprises a plurality of half cells adjacent to a boundary of the merging cell.
14. 14. The semiconductor device according to claim 1, wherein the merging unit includes a first merging unit and a second merging unit adjacent to each other in the second direction and located between the first half unit and the second half unit, Wherein, the each of the first merging unit and the second merging unit each comprising said first active pattern and said second active pattern, and Wherein the first half cell is adjacent to a first active pattern of the first merging cell and the second half cell is adjacent to a second active pattern of the second merging cell.
15. 15. The semiconductor device according to claim 1, wherein the merging unit includes a first merging unit and a second merging unit adjacent to each other in the first direction and located between the first half unit and the second half unit, and Wherein the first half unit is adjacent to a first active pattern of the first and second merging units, and the second half unit is adjacent to a second active pattern of the first and second merging units.
16. 16. A semiconductor device, comprising: first to third rows each including a first conductive type active pattern and a second conductive type active pattern extending in a first direction and arranged in a second direction intersecting the first direction, wherein the first conductive type active pattern and the second conductive type active pattern of the second row are adjacent to the first conductive type active pattern of the first row and the second conductive type active pattern of the third row, respectively; a merging unit located in the second row and extending in a first region of each of the first and third rows adjacent to the second row, the merging unit including a first merged active pattern in which the first conductive type active pattern of the first row and the first conductive type active pattern of the second row are merged, and a second merged active pattern in which the second conductive type active pattern of the second row and the second conductive type active pattern of the third row are merged; a first half unit overlapping the merging unit in the second direction and extending in a second region of the first row, the first half unit including the second conductive type active pattern of the first row, and A second half unit overlapping the merging unit in the second direction and extending in a second region of the third row, the second half unit including the first conductive type active pattern of the third row, Wherein the merging unit includes a first conductivity type transistor on the first merged active pattern and a second conductivity type transistor on the second merged active pattern, and Wherein at least one of the first half cell and the second half cell includes a transistor or a capacitor on the second conductive type active pattern of the first row or the first conductive type active pattern of the third row.
17. 17. The semiconductor device according to claim 16, wherein the first line to the third line each have the same height in the second direction, and Wherein the merging unit has a first unit height in the second direction that is twice the height, and the first half unit and the second half unit have a second unit height and a third unit height in the second direction that are half the height, respectively.
18. 18. The semiconductor device according to claim 16, wherein a width of each of the first and second merged active patterns in the second direction is greater than twice a width of each of the first and second conductive type active patterns of the third row in the second direction.
19. 19. A semiconductor device, comprising: A merging unit including a first active pattern and a second active pattern extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the merging unit further including a first p-type transistor on the first active pattern and a first n-type transistor on the second active pattern; A first half cell adjacent to the first active pattern of the merging cell in the second direction and including a third active pattern extending in the first direction, the first half cell further including a second n-type transistor on the third active pattern, and A second half cell adjacent to the second active pattern of the merging cell in the second direction and including a fourth active pattern extending in the first direction, the second half cell further including a second p-type transistor on the fourth active pattern, Wherein the merging unit has a first unit height in the second direction, and the first half unit and the second half unit each have a second unit height smaller than the first unit height in the second direction, and Wherein each of the first and second active patterns has a first width in the second direction, and each of the third and fourth active patterns has a second width smaller than the first width in the second direction.
20. 20. The semiconductor device of claim 19, wherein the merging unit further comprises a first gate line crossing the first active pattern and the second active pattern and extending in the second direction, Wherein the first half unit further includes a second gate line crossing the third active pattern and extending in the second direction, Wherein the second half unit further includes a third gate line crossing the fourth active pattern and extending in the second direction, and The semiconductor device further includes a first gate isolation pattern separating the first gate line from the second gate line between the merging unit and the first half unit, and a second gate isolation pattern separating the first gate line from the third gate line between the merging unit and the second half unit.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Cross Reference to Related Applications The present application claims the benefit of priority from korean patent application No.10-2024-0159920 filed in the korean intellectual property office on day 11 and 12 of 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field The present disclosure relates to semiconductor devices. Background As the demand for high performance, high speed, and/or versatility of semiconductor devices has increased, the integration of semiconductor devices has also increased. As the integration of the semiconductor device increases, the operation characteristics of the semiconductor device may deteriorate. Accordingly, various methods are being studied to form semiconductor devices with better performance while overcoming the limitation of the integration level of the semiconductor devices. In order to overcome limitations in operation characteristics due to scaling down, efforts are being made to develop a semiconductor device including a transistor having a three-dimensional (3D) channel structure. Disclosure of Invention Aspects of the present disclosure provide a semiconductor device that facilitates high integration while maintaining operational characteristics. According to some aspects of the present disclosure, a semiconductor device includes a merging unit including first and second active patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the merging unit further including first p-type transistors on the first active patterns and first n-type transistors on the second active patterns, a first half unit adjacent to the first active patterns of the merging unit in the second direction and including third active patterns extending in the first direction, a second half unit adjacent to the second active patterns of the merging unit in the second direction and including fourth active patterns extending in the first direction, and a logic circuit element located on at least one of the third active patterns and the fourth active patterns, wherein the merging unit has a first cell height in the second direction and each of the first half unit and the second half unit has a second cell height smaller than the first cell height in the second direction, and wherein the first and second active patterns have a width in each of the first and second active patterns in the first direction smaller than each of the first active patterns and the second active patterns in the first direction. According to some aspects of the present disclosure, a semiconductor device includes first to third rows each including a first conductive type active pattern and a second conductive type active pattern extending in a first direction and arranged in a second direction intersecting the first direction, wherein the first conductive type active pattern and the second conductive type active pattern of the second row are adjacent to the second conductive type active pattern of the first row and the second conductive type active pattern of the third row, respectively, a merging unit located in the second row and extending in a first region of each of the first and third rows adjacent to the second row, the merging unit including a first merging active pattern and a second merging active pattern in which the first conductive type active pattern of the first row and the first conductive type active pattern of the second row are merged, in which the second conductive type active pattern of the second row and the second conductive type active pattern of the third row are merged, respectively, a second semiconductor unit located in the second row and extending in a first region of each of the first and third rows adjacent to the second row, wherein the merging unit includes a first merging active pattern and a second merging active pattern, the first conductive type active pattern of the first row and the second line is merged, the second conductive type active pattern of the first row is overlapped with the second semiconductor unit in the first direction, the second semiconductor unit is overlapped with the first semiconductor unit and the first semiconductor unit is overlapped with the first semiconductor unit in the first region, at least one of the first half cell and the second half cell includes a transistor or a capacitor on the second conductive type active pattern of the first row or the first conductive type active pattern of the third row. According to some aspects of the present disclosure, a semiconductor device includes a merging unit including first and second active patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the merging unit further including first p-type transistors on the first active pattern and first n