CN-122028504-A - Semiconductor layout pattern and method for manufacturing the same

CN122028504ACN 122028504 ACN122028504 ACN 122028504ACN-122028504-A

Abstract

The invention discloses a semiconductor layout pattern and a manufacturing method thereof, wherein the semiconductor layout pattern comprises a substrate, two content addressable memory (Content Addressable Memory, CAM) units are arranged on two sides of a symmetry axis on the substrate, and a first match line (MATCHING LINE, ML) conductive layer and a second match line conductive layer are arranged on the substrate, wherein the first match line conductive layer and the second match line conductive layer are overlapped with the symmetry axis between the two content addressable memory units in a top view and are arranged along the direction of the symmetry axis.

Inventors

ZENG JUNYAN
HUANG JUNXIAN
GUO YOUCE
WANG SHURU
LIN JUNXIAN
ZHUANG MENGPING

Assignees

联华电子股份有限公司

Dates

Publication Date: 20260512
Application Date: 20241121
Priority Date: 20241108

Claims (20)

1. A semiconductor layout pattern, comprising: A substrate having two content addressable memory (Content Addressable Memory, CAM) cells arranged on both sides of the symmetry axis, and A first match line (MATCHING LINE, ML) conductive layer and a second match line conductive layer are on the substrate, wherein the first match line conductive layer and the second match line conductive layer overlap the symmetry axis between the two content addressable memory cells and are aligned along the direction of the symmetry axis as viewed from a top view.
2. The semiconductor layout pattern as claimed in claim 1, wherein each of the content addressable memory cells comprises four sides, wherein one side is the symmetry axis, three sides other than the symmetry axis are defined as outer boundaries, and the first match line conductive layer and the second match line conductive layer do not overlap with the three outer boundaries.
3. The semiconductor layout pattern of claim 1 wherein each content addressable memory cell comprises ten transistor layout patterns, and each ten transistor layout pattern comprises: The first pull-up transistor (PU 1) and the first pull-down transistor (PD 1) constitute a first inverter (INV 1); the second pull-up transistor (PU 2) and the second pull-down transistor (PD 2) form a second inverter (INV 2); a first pass gate transistor (PG 1) and a second pass gate transistor (PG 2) connecting the first inverter and the second inverter, and A first transistor and a second transistor connected in series, wherein the gate structure of the first transistor is connected to the gate structure of the first pull-down transistor (PD 1), and And a third transistor and a fourth transistor connected in series, wherein the gate structure of the fourth transistor is connected to the gate structure of the second pull-down transistor (PD 2).
4. The semiconductor layout pattern as claimed in claim 3, wherein the gate of the second transistor and the gate of the third transistor are connected to a search line SL1 and another search line SL1B, respectively.
5. The semiconductor layout pattern according to claim 3, wherein a source of the second transistor and a source of the fourth transistor are connected to a Match Line (ML).
6. The semiconductor layout pattern as recited in claim 3, wherein a drain of the first transistor and a drain of the third transistor are connected to a voltage source (Vss).
7. The semiconductor layout pattern of claim 1 wherein, in a horizontal direction, the first match line conductive layer, bit line conductive layer, vcc voltage source conductive layer, vss voltage source conductive layer, and the second match line conductive layer are sequentially included along the axis of symmetry between the two content addressable memory cells in the top view.
8. The semiconductor layout pattern as claimed in claim 1, further comprising a second metal layer, wherein the second metal layer comprises a first portion, the first portion is a stripe pattern extending along a horizontal direction, and the first portion is electrically connected to the first match line conductive layer and the second match line conductive layer.
9. The semiconductor layout pattern of claim 8 wherein one of the two content addressable memory cells comprises an upper boundary, wherein the upper boundary of the content addressable memory cell comprises, in order along a horizontal direction, a first Vss voltage supply conductive layer, a second Vss voltage supply conductive layer, a Vcc voltage supply conductive layer, a bit line conductive layer, and a third Vss voltage supply conductive layer.
10. The semiconductor layout pattern of claim 9 wherein the second metal layer comprises a second portion which is a stripe pattern extending along a horizontal direction and overlaps the upper boundary, wherein the second portion is electrically connected to the first Vss voltage source conductive layer, the second Vss voltage source conductive layer, and the third Vss voltage source conductive layer.
11. A method for manufacturing a semiconductor layout pattern includes: providing a substrate having two content addressable memory (Content Addressable Memory, CAM) cells formed thereon and arranged on opposite sides of an axis of symmetry, and A first match line (MATCHING LINE, ML) conductive layer and a second match line conductive layer are formed on the substrate, wherein the first match line conductive layer and the second match line conductive layer overlap the symmetry axis between the two content addressable memory cells and are aligned along the direction of the symmetry axis as seen from a top view.
12. The method of claim 11, wherein each of the content addressable memory cells includes four sides, one of the sides is the symmetry axis, three sides other than the symmetry axis are defined as outer boundaries, and the first and second match line conductive layers do not overlap the three outer boundaries.
13. The method of claim 11, wherein each content addressable memory cell comprises ten transistor layout patterns, and each ten transistor layout pattern comprises: The first pull-up transistor (PU 1) and the first pull-down transistor (PD 1) constitute a first inverter (INV 1); the second pull-up transistor (PU 2) and the second pull-down transistor (PD 2) form a second inverter (INV 2); a first pass gate transistor (PG 1) and a second pass gate transistor (PG 2) connecting the first inverter and the second inverter, and A first transistor and a second transistor connected in series, wherein the gate structure of the first transistor is connected to the gate structure of the first pull-down transistor (PD 1), and And a third transistor and a fourth transistor connected in series, wherein the gate structure of the fourth transistor is connected to the gate structure of the second pull-down transistor (PD 2).
14. The method of claim 13, wherein the gate of the second transistor and the gate of the third transistor are respectively connected to a search line SL1 and another search line SL1B.
15. The method of claim 13, wherein the source of the second transistor and the source of the fourth transistor are connected to a Match Line (ML).
16. The method of claim 11, wherein the drain of the first transistor and the drain of the third transistor are connected to a voltage source (Vss).
17. The method of claim 11, wherein the first match line conductive layer, the bit line conductive layer, the Vcc voltage source conductive layer, the Vss voltage source conductive layer, and the second match line conductive layer are sequentially included along the symmetry axis between the two content addressable memory cells in a horizontal direction as viewed from the top.
18. The method of claim 11, further comprising forming a second metal layer, wherein the second metal layer includes a first portion, the first portion is a stripe pattern extending along a horizontal direction, and the first portion is electrically connected to the first and second match line conductive layers.
19. The method of claim 18, wherein one of the two CAM cells includes an upper boundary, wherein the upper boundary of the CAM cell includes a first Vss voltage source conductive layer, a second Vss voltage source conductive layer, a Vcc voltage source conductive layer, a bit line conductive layer, and a third Vss voltage source conductive layer in order along a horizontal direction.
20. The method of claim 19, wherein the second metal layer comprises a second portion, the second portion being a stripe pattern extending along a horizontal direction and overlapping the upper boundary, wherein the second portion is electrically connected to the first Vss voltage source conductive layer, the second Vss voltage source conductive layer, and the third Vss voltage source conductive layer.

Description

Semiconductor layout pattern and method for manufacturing the same Technical Field The present invention relates to the field of semiconductors, and more particularly, to a layout pattern for a content addressable memory (Content Addressable Memory, CAM) and a method of making the same. Background In general, when performing digital data operations, it is difficult to achieve instant data query processing because the amount of data to be processed is quite large, and the stored data of some applications (such as routers of networks) need to be dynamically updated in large amounts, and the stored data cannot be ordered in advance. In order to effectively speed up the searching of data for these large and randomly stored data, a content addressable memory (Content Addressable Memory, CAM) has been employed to solve various searching problems. The content addressable memory (also called a associative memory) looks like a huge lookup table (lookup table), can find out the address of the key according to the input key, by using the special hardware architecture design of CAM, the key words to be searched can be simultaneously compared with the data in the CAM, and the data addresses conforming to the input key words are output, so that the data associated with the key words can be found by utilizing the key word addresses found by the CAM. The content addressable memory may comprise Binary Content Addressable Memory (BCAM) and ternary content addressable memory (TERNARY CAM, TCAM). Each bit in the BCAM has two states, 0 or 1, and each bit in the ternary content addressable memory has three states, namely a don't care state in addition to 0 and 1, so that the ternary content addressable memory is called a ternary state, and the third state feature of the TCAM enables the ternary content addressable memory to perform both exact match search and fuzzy match search. Disclosure of Invention The invention provides a semiconductor layout pattern, comprising a substrate, two content addressable memory (Content Addressable Memory, CAM) units are arranged on two sides of a symmetry axis, and a first match line (MATCHING LINE, ML) conductive layer and a second match line conductive layer are arranged on the substrate, wherein the first match line conductive layer and the second match line conductive layer are overlapped with the symmetry axis between the two content addressable memory units in a top view and are arranged along the direction of the symmetry axis. The invention further provides a method for fabricating a semiconductor layout pattern, which comprises providing a substrate on which two content addressable memory (Content Addressable Memory, CAM) cells are formed on both sides of a symmetry axis, and forming a first match line (MATCHING LINE, ML) conductive layer and a second match line conductive layer on the substrate, wherein the first match line conductive layer and the second match line conductive layer overlap the symmetry axis between the two content addressable memory cells from a top view and are arranged along the direction of the symmetry axis. The invention is characterized in that a layout pattern of a ten-transistor unit and a corresponding circuit diagram are provided. In another embodiment of the present invention, the conductive layers connecting the match lines in each region are aligned in the same direction to reduce the number of conductive line structures passing through each region, thereby allowing each region to be more closely aligned to reduce the device area. Drawings Fig. 1 is a schematic diagram of circuit patterns of two adjacently arranged ten-transistor units in a first embodiment of the present invention; FIG. 2 is a schematic diagram showing a layout pattern of two adjacent ten transistor cells according to a first embodiment of the present invention; FIG. 3 is a schematic top view of a plurality of regions including ten transistor cells and conductive lines connecting match lines according to a first embodiment of the present invention; Fig. 4 is a schematic diagram of circuit patterns of two adjacently arranged ten-transistor units in a second embodiment of the present invention; fig. 5, 6 and 7 are schematic diagrams showing layout patterns of two adjacent ten-transistor cells according to a second embodiment of the present invention; fig. 8 is a schematic top view of a plurality of regions including ten transistor cells and conductive lines connecting match lines according to a second embodiment of the present invention. Symbol description Ten transistor unit (content addressable memory) Ten transistor units (content addressable memory) Ten transistor unit (content addressable memory) Ten transistor units (content addressable memory) 6T-SRAM six transistor static random access memory BL bit line BLB bit line E1:boundary line (symmetry axis) F: fin-like structure G: grid structure INV1 first inverter INV2 second inverter L1: wire structure L2 wire structure L3:conductor str