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CN-122028505-A - ESD device

CN122028505ACN 122028505 ACN122028505 ACN 122028505ACN-122028505-A

Abstract

The present application provides an ESD device comprising: the application sets the main polysilicon layer on the substrate as a snake shape, and increases PN junction area at the snake-shaped bent angle (each corner) at the same time of keeping the original transverse PN junction area, thereby effectively improving the PN junction area of ESD through-flow of the ESD device under the condition of keeping the whole size (chip occupation area) of the PN junction diode unchanged, namely effectively improving the ESD performance of the device.

Inventors

  • FAN WEISHENG

Assignees

  • 华虹半导体(无锡)有限公司

Dates

Publication Date
20260512
Application Date
20260121

Claims (9)

  1. 1. An ESD device, comprising: A substrate; a plurality of main polysilicon layers having a serpentine shape in a top view are disposed on the substrate at intervals; a well region of a first conductivity type located in the substrate at the bottom of the bulk polysilicon layer; a plurality of first heavily doped regions of a first conductivity type and a plurality of second heavily doped regions of a second conductivity type, wherein the first heavily doped regions and the second heavily doped regions are respectively positioned in the substrates at two sides of each main body polysilicon layer, and two adjacent main body polysilicon layers share the same first heavily doped region or the same second heavily doped region; The well region and the first heavily doped region are both connected with a cathode of an external power supply, and the second heavily doped region is connected with an anode of the external power supply.
  2. 2. The ESD device of claim 1 wherein the substrate comprises bottom silicon, an intermediate oxide layer and top silicon, the intermediate oxide layer being on the bottom silicon and the top silicon being on the intermediate oxide layer, wherein the well region, the first heavily doped region and the second heavily doped region are all in the top silicon.
  3. 3. The ESD device of claim 1 wherein each of said body polysilicon layers has a serpentine shape in plan view comprising a plurality of polysilicon sublayers of the bracketed type, all of said polysilicon sublayers being joined end to end in sequence with bracket openings of adjacent two of said polysilicon sublayers facing opposite directions.
  4. 4. The ESD device of claim 3 wherein each of the body polysilicon layers having a serpentine shape in plan view has a minimum width of 0.3 μm to 0.5 μm in the X direction, a width of 0.2 μm to 0.5 μm in the Y direction, and a lateral dimension at a corner of the polysilicon sub-layer between brackets of 0.35 μm to 0.6 μm.
  5. 5. The ESD device of claim 3 further comprising an interlayer dielectric layer, a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the interlayer dielectric layer covers the main polysilicon layer, the first heavily doped region and the second heavily doped region near the surface of the substrate, a plurality of first conductive plugs penetrate the interlayer dielectric layer and are in contact with the first heavily doped region, and a plurality of second conductive plugs penetrate the interlayer dielectric layer and are in contact with the second heavily doped region.
  6. 6. The ESD device of claim 5 wherein each of said body polysilicon layers having a serpentine shape in plan view has one of said first conductive plug and said second conductive plug disposed within a bracket opening of each of said polysilicon sublayers.
  7. 7. The ESD device of claim 1 further comprising an auxiliary polysilicon layer on the substrate on either the head or tail side of the main polysilicon layer, and connecting the head ends of all the main polysilicon layers or the tail ends of all the main polysilicon layers.
  8. 8. The ESD device of claim 7 further comprising a plurality of third conductive plugs extending through the interlayer dielectric layer and contacting the auxiliary polysilicon layer.
  9. 9. The ESD device of claim 1 wherein the first conductivity type is N-type and the second conductivity type is P-type.

Description

ESD device Technical Field The application relates to the technical field of integrated circuit manufacturing, in particular to an ESD device. Background In SOI (Silicon-On-Insulator) platforms, the ESD device can adapt to the middle oxide isolation characteristics of SOI because the middle layer of the substrate is an insulating oxide, avoiding the substrate coupling and latch-up risks common in bulk Silicon. However, due to the limited thickness of the top silicon layer above the intermediate oxide layer, the n+/p+ ions of the top silicon layer are directly contacted with the intermediate oxide layer of the substrate after being implanted, so that the SOI platform is lack of a longitudinal PN junction compared with the bulk silicon platform, and therefore, the GGNMOS device or GDPMOS device of the platform has no ESD (Electrostatic Discharge ) capability basically, and a common solution of the SOI platform ESD is to use a transverse PN junction (diode) to realize rapid discharging and voltage clamping of electrostatic pulses. Because of the limited thickness of the top silicon layer and the smaller lateral PN junction area of the traditional ESD device based on SOI platform, in order to improve ESD capability, the current conventional method is to increase the size of the lateral PN junction (diode), but this will increase the chip area, which does not meet the requirement of higher and higher device integration level. Disclosure of Invention The application provides an ESD device, which can solve at least one of the problems of poor current discharge capability, large transverse PN junction area and the like of an ESD device based on an SOI platform. The embodiment of the application provides an ESD device, which comprises: A substrate; a plurality of main polysilicon layers having a serpentine shape in a top view are disposed on the substrate at intervals; a well region of a first conductivity type located in the substrate at the bottom of the bulk polysilicon layer; a plurality of first heavily doped regions of a first conductivity type and a plurality of second heavily doped regions of a second conductivity type, wherein the first heavily doped regions and the second heavily doped regions are respectively positioned in the substrates at two sides of each main body polysilicon layer, and two adjacent main body polysilicon layers share the same first heavily doped region or the same second heavily doped region; The well region and the first heavily doped region are both connected with a cathode of an external power supply, and the second heavily doped region is connected with an anode of the external power supply. Optionally, in the ESD device, the substrate includes a bottom silicon, an intermediate oxide layer and a top silicon, the intermediate oxide layer is located on the bottom silicon, and the top silicon is located on the intermediate oxide layer, wherein the well region, the first heavily doped region and the second heavily doped region are all located in the top silicon. Optionally, in the ESD device, each of the main polysilicon layers having a serpentine shape in a top view includes a plurality of polysilicon sub-layers having a bracket shape, all of the polysilicon sub-layers are sequentially connected end to end, and bracket openings of two adjacent polysilicon sub-layers face opposite directions. Optionally, in the ESD device, a minimum width of the polysilicon sub-layer along the X direction is 0.3 μm to 0.5 μm, a width of the polysilicon sub-layer along the Y direction is 0.2 μm to 0.5 μm, and a lateral dimension of the polysilicon sub-layer at a corner between brackets is 0.35 μm to 0.6 μm in each of the main polysilicon layers having a serpentine shape in a top view. Optionally, in the ESD device, the ESD device further comprises an interlayer dielectric layer, a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the interlayer dielectric layer covers the main polysilicon layer, the first heavily doped region and the second heavily doped region close to the surface of the substrate, the plurality of first conductive plugs penetrate through the interlayer dielectric layer and are in contact with the first heavily doped region, and the plurality of second conductive plugs penetrate through the interlayer dielectric layer and are in contact with the second heavily doped region. Optionally, in the ESD device, in each of the main polysilicon layers having a serpentine shape in a top view, one of the first conductive plug and the second conductive plug is disposed in a bracket opening of each of the polysilicon sublayers. Optionally, in the ESD device, the ESD device further comprises an auxiliary polysilicon layer, wherein the auxiliary polysilicon layer is positioned on the substrate at the head end or tail end side of the main polysilicon layer, and the auxiliary polysilicon layer connects the head ends of all the main polysilicon layers or connects t