CN-122028507-A - ESD device of MOS structure

Abstract

The invention discloses an ESD device with a MOS structure, which is positioned in a P well and comprises a drain region positioned in the center and source regions symmetrically arranged at two sides of the drain region, wherein the surface of a semiconductor substrate or an epitaxial layer between the source region and the drain region is provided with a grid structure, two ends of a heavily doped drain region are respectively provided with an independent heavily doped P-type injection region on a top plane, and an adjustable distance D is arranged between the heavily doped P-type injection region and the heavily doped drain region. When the breakdown voltage of the parasitic diode is smaller than the breakdown voltage between the heavily doped drain region and the P well, the parasitic diode is broken down first under the ESD condition, and the effect of reducing the trigger voltage of the NMOS is achieved. The structure does not need to increase any photoetching plate, implantation process and device area, and does not increase the cost.

Inventors

• FAN WEISHENG

Assignees

• 华虹半导体(无锡)有限公司

Dates

Publication Date

20260512

Application Date

20260130

Claims (8)

1. 1. An ESD device with a MOS structure is characterized in that the ESD device is positioned in a P well and comprises a drain region positioned at the center and source regions symmetrically arranged at two sides of the drain region, wherein the surface of a semiconductor substrate or an epitaxial layer between the source region and the drain region is provided with a grid structure; On the top plane, two ends of the heavily doped drain region are respectively provided with an independent heavily doped P-type injection region, and an adjustable distance D is arranged between the heavily doped P-type injection region and the heavily doped drain region.
2. 2. The ESD device of the MOS structure of claim 1 wherein the substrate comprises a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate, a silicon carbide substrate.
3. 3. The ESD device of the MOS structure of claim 1 wherein the surface of the substrate above the drain region and the side and part of the surface of the gate structure adjacent to the drain region are further covered with an SAB dielectric layer.
4. 4. The ESD device of claim 1 wherein the gate structure comprises a gate dielectric layer overlying the semiconductor substrate or epitaxial layer, and a gate conductive material layer overlying the gate dielectric layer.
5. 5. The ESD device of claim 3 wherein the heavily doped P-type injection region and the heavily doped drain region are in the same active region to form a parasitic diode, and the SAB dielectric layer is effective for preventing short circuit between the two due to metal silicide.
6. 6. The ESD device of claim 5 wherein the parasitic diode has a breakdown voltage smaller than that between the drain region and the P-well, and the parasitic diode will breakdown first in the case of ESD to reduce the trigger voltage of NMOS.
7. 7. The ESD device of claim 1 wherein the heavily doped P-type implant region structure is formed at both ends of the drain region without increasing any photolithography, implantation process and device area.
8. 8. The ESD device of claim 1 wherein the distance D has a length that is capable of adjusting the breakdown voltage of the parasitic diode of the ESD device.

Description

ESD device of MOS structure Technical Field The invention relates to the field of semiconductor device manufacturing, in particular to an ESD device with a MOS structure. Background MOS is used as a common ESD device and is commonly used for ESD protection of a power port and an I/O port, and the main principle is to start and discharge ESD current by utilizing an NPN parasitic by Drain/PW/Source. However, as the advanced process node is gradually advanced, the length of the channel is shorter and shorter, the thickness of the gate oxide serving as the gate dielectric layer is thinner and thinner, the breakdown voltage is further reduced, the trigger voltage of the MOS is close to or even smaller than the breakdown voltage of the gate oxide, and the protected gate oxide is broken down in advance under the condition that the ESD device is not started, so that the effect of protecting the gate oxide is completely absent. A common improvement measure is to increase one ESD injection to reduce the trigger voltage of the ESD MOS transistor, but this increases one photolithography and injection process, and increases the manufacturing cost. Disclosure of Invention The invention aims to solve the technical problem of providing an ESD device with a MOS structure, and to solve the problem that the ESD protection device is broken down first under certain conditions and cannot provide an ESD protection function. In order to solve the problems, the invention provides an ESD device with a MOS structure, which is positioned in a P well in a semiconductor substrate and comprises a drain region positioned at the center and source regions positioned at two sides of the drain region and forming symmetry, wherein the surface of the substrate between the source region and the drain region is provided with a grid structure; On the top plane, two ends of the heavily doped drain region are respectively provided with an independent heavily doped P-type injection region, and an adjustable distance D is arranged between the heavily doped P-type injection region and the heavily doped drain region. Further, the semiconductor substrate comprises a silicon substrate, a germanium-silicon substrate, a gallium arsenide substrate, a gallium nitride substrate and a silicon carbide substrate. Further, the surface of the substrate above the drain region and the side surface and part of the surface of the gate structure close to the drain region are also covered with an SAB dielectric layer. Furthermore, the heavily doped P-type injection region and the heavily doped drain region are positioned in the same active region to form a parasitic diode, and the SAB dielectric layer can effectively prevent short circuit between the heavily doped P-type injection region and the heavily doped drain region caused by metal silicide. Further, when the breakdown voltage of the parasitic Diode is smaller than the breakdown voltage between the drain region and the P well, the parasitic Diode breaks down first under the ESD condition, and the effect of reducing the trigger voltage of the NMOS is achieved. Further, the heavily doped P-type implanted region structure at both ends of the drain region does not require any additional photolithography, implantation process and device area. Further, the distance D can adjust the breakdown voltage of the parasitic diode. The invention provides an ESD device with a MOS structure, wherein partial N+ doped regions at two ends above and below a drain region are replaced by P+ doped regions, the N+ doped regions and the P+ doped regions keep a certain distance D to form a parasitic diode, the breakdown voltage of the parasitic diode can be changed by adjusting the distance D between the N+ doped regions and the P+ doped regions, and when the breakdown voltage of the parasitic diode is smaller than the breakdown voltage between the N+ doped regions and PW, the parasitic diode is broken down first under the condition of ESD, so that the effect of reducing the trigger voltage of NMOS is achieved. The structure does not need to increase any photoetching plate, implantation process and device area, and does not increase the cost. Drawings Fig. 1 is a schematic plan view and a schematic longitudinal section of an ESD device structure according to the present invention. Fig. 2 is a schematic diagram of the connection of ports of the ESD device of the present invention when ESD testing is performed. Fig. 3 is a plot of the breakdown voltage and trigger voltage of the ESD device of the present invention as a function of pitch D. FIG. 4 is a graph of DC/TLP testing performed on a device of the present invention. Detailed Description The following description of the embodiments of the present invention will be given with reference to the accompanying drawings, in which the technical solutions of the present invention are clearly and completely described, but the present invention is not limited to the following embodiments. It will be