CN-122028529-A - Image sensor and pixel with trench isolation structure

Abstract

The invention provides an image sensor with a trench isolation structure and a pixel, wherein the image sensor comprises a plurality of pixels and a plurality of deep trench isolation pieces formed among the pixels. The deep trench spacers include a plurality of back side deep trench spacers extending from the back side of the substrate and surrounding the photodiodes and floating diffusions of the corresponding pixels from the outside, and a plurality of front side deep trench spacers extending from the front surface of the substrate and having lower ends facing portions of the upper ends of the back side deep trench spacers.

Inventors

• Fukuoka Shinra
• Cao Guannuo

Assignees

• 豪威科技股份有限公司

Dates

Publication Date

20260512

Application Date

20250513

Priority Date

20241111

Claims (20)

1. 1. An image sensor is provided, which is capable of detecting a light source, characterized by comprising the following steps: A plurality of pixels, and A plurality of deep trench spacers formed between the plurality of pixels, wherein each of the plurality of pixels comprises: A photodiode; Floating diffusion region, and A transfer gate coupling the photodiode and the floating diffusion region, wherein The plurality of deep trench spacers includes: a plurality of backside deep trench spacers extending from the back side of the substrate, wherein the plurality of backside deep trench spacers respectively surround the photodiodes and the floating diffusion regions of adjacent pixels of the plurality of pixels, thereby defining a pixel region for a corresponding one of the plurality of pixels, A plurality of front side deep trench spacers extending from the front surface of the substrate and having a lower end facing a portion of the upper ends of the plurality of back side deep trench spacers.
2. 2. The image sensor of claim 1, wherein: each of the plurality of pixels is square in a plan view along a direction plane parallel to the front surface of the substrate, and Portions of the plurality of backside deep trench spacers corresponding to corners of the pixel region have a partial depth, upper ends of the portions thereof terminate at a middle portion of the substrate, and the plurality of front side deep trench spacers are formed to face the upper ends.
3. 3. The image sensor of claim 2, wherein: The portions of the plurality of backside deep trench spacers other than the corners of the pixel region have a full depth extending from the back surface to the front surface of the substrate.
4. 4. The image sensor of claim 1, wherein the plurality of front side deep trench spacers and the plurality of back side deep trench spacers are formed of different materials.
5. 5. The image sensor of claim 1, wherein each of the plurality of front side deep trench spacers comprises a polysilicon material and each of the plurality of back side deep trench spacers comprises a dielectric material.
6. 6. The image sensor of claim 1, wherein the photodiode comprises a photodiode doped region having a first conductivity type, and A low-concentration impurity doped region having a second conductivity type is provided, the second conductivity type being opposite to the first conductivity type of the photodiode doped region, and the low-concentration impurity doped region being disposed adjacent to a side of the plurality of front-side deep trench spacers.
7. 7. The image sensor of claim 6, wherein the low concentration impurity doped region comprises a portion disposed between the photodiode doped region and a corresponding front side deep trench isolation included in the plurality of front side deep trench isolation members.
8. 8. The image sensor of claim 1, wherein the plurality of front side deep trench isolations are coupled to receive a ground reference voltage.
9. 9. The image sensor of claim 1, wherein each of the plurality of backside deep trench spacers is vertically aligned with a respective one of the plurality of front side deep trench spacers and collectively defines a pixel region for each of the plurality of pixels.
10. 10. The image sensor of claim 1, wherein a cross-sectional width of a lower end of one of the plurality of front side deep trench spacers is greater than a cross-sectional width of the upper end of a corresponding one of the plurality of back side deep trench spacers.
11. 11. The image sensor of claim 1, wherein each of the plurality of front side deep trench spacers is formed of a polysilicon material.
12. 12. The image sensor of claim 1, wherein a lower end of a respective one of the plurality of front side deep trench spacers is in direct contact with an upper end of a respective one of the plurality of back side deep trench spacers.
13. 13. A pixel, comprising: a photodiode disposed in a semiconductor material having a front side surface and a back side opposite the front side surface; A floating diffusion region disposed in the semiconductor material, and A transfer gate configured to couple the photodiode and the floating diffusion region, wherein the isolation structure comprises: A backside deep trench isolation extending from the backside of the semiconductor material to the front side surface of the semiconductor material, wherein the backside deep trench isolation surrounds the photodiode and the floating diffusion region, thereby defining a pixel region for the pixel, Wherein the backside deep trench isolation has a first portion and a second portion, the first portion being located at a corner region of the pixel region and the second portion being located at a non-corner region of the pixel region, Wherein the first portion of the backside deep trench isolation has a first depth relative to the backside of the semiconductor material that is less than a second depth of the second portion of the backside deep trench isolation.
14. 14. The pixel of claim 13, wherein the second depth of the second portion is equal to a vertical thickness of the semiconductor material.
15. 15. The pixel of claim 13, wherein the isolation structure further comprises a front side deep trench isolation extending from the front side surface of the semiconductor material into the semiconductor material, wherein the front side deep trench isolation extends into direct contact with the first portion of the back side deep trench isolation.
16. 16. The pixel of claim 15, wherein the transfer gate comprises a vertical transfer gate extending from the front side surface into the semiconductor material, wherein the vertical transfer gate has a gate depth that is less than a front isolation depth of the isolation structure.
17. 17. The pixel of claim 15, wherein the front side deep trench isolation comprises a trench filled with an impurity-filled polysilicon material and the back side deep trench isolation comprises a trench at least partially filled with a dielectric material.
18. 18. The pixel of claim 17, wherein the polysilicon material of the front side deep trench isolation is coupled to receive a ground reference voltage.
19. 19. The pixel of claim 18, further comprising: An impurity doped region disposed in the semiconductor material and surrounding the front side deep trench isolation.
20. 20. The pixel of claim 19, wherein the impurity doped region is coupled to the polysilicon material of the front side deep trench isolation to receive the ground reference voltage.

Description

Image sensor and pixel with trench isolation structure Technical Field The present invention relates to an image sensor including a deep trench isolation formed between a plurality of pixels, and more particularly, to an image sensor having a trench isolation structure and a pixel. Background In an image sensor, various measures are taken to reduce the size of pixels. For example, a system employing a three wafer stack of pixel wafers for a photodiode array, transistor wafers for pixel transistors (including reset, source follower, and row select transistors), and logic wafers for application-specific integrated circuit (ASIC) circuits. However, further reduction of pixels is required. In smaller pixels, it is difficult to balance Full well capacity (Full WELL CAPACITY, FWC) and halo (bloom) performance. That is, in order to prevent halation from occurring between adjacent pixels within a smaller pixel, the FWC is set low. In order to prevent crosstalk between pixels, sufficient isolation between adjacent pixels is required. For this purpose, for example, a Deep Trench Isolation (DTI) structure between pixels is used. In the DTI structure, the pixels are isolated by trenches extending in the depth direction of the substrate. Here, the ground contact region is disposed near the substrate surface, an opening portion is provided between the ground contact region and the DTI structure, and crosstalk may occur in this region. Disclosure of Invention An image sensor according to the present invention includes a plurality of pixels, each including a photodiode, a floating diffusion, and a transfer gate connecting the photodiode and the floating diffusion, and a Deep Trench Isolation (DTI) formed between the plurality of pixels, the deep trench isolation including a plurality of back side deep trench isolation (back side deep trenchisolation, BDTI) extending from a back side of a substrate and surrounding the photodiode and the floating diffusion of the corresponding pixel from outside, and a plurality of front side deep trench isolation (front SIDE DEEP TRENCH isolation, FDTI) extending from a front surface of the substrate and having a lower end facing a portion of an upper end of BDTI. A pixel according to the invention includes a photodiode and a floating diffusion region disposed in a semiconductor material and a transfer gate disposed to couple the photodiode and the floating diffusion region, the isolation structure includes a backside deep trench isolation extending from a backside of the semiconductor material to a front side surface of the semiconductor material, the backside deep trench isolation surrounding the photodiode and the floating diffusion region to define a pixel region for the pixel, the backside deep trench isolation having a first portion and a second portion, the first portion being located at a corner region of the pixel region and the second portion being located at a non-corner landing region of the pixel region, the first portion of the backside deep trench isolation having a first depth relative to the backside of the semiconductor material that is less than a second depth of the second portion of the backside deep trench isolation. According to the image sensor of the present invention, crosstalk can be effectively suppressed by BDTI and FDTI. Drawings Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein the same or similar reference numerals are used to designate the same or similar components, unless otherwise specified: FIG. 1A is a schematic plan view showing a partial structure of an image sensor according to the teachings of the present invention; FIG. 1B is a schematic cross-sectional view along line X-X in FIG. 1A, in accordance with the teachings of the present invention; FIG. 1C is a schematic enlarged view of portion A in FIG. 1B, according to the teachings of the present invention; FIG. 1D is a schematic cross-sectional view along line Y-Y in FIG. 1A, in accordance with the teachings of the present invention; FIG. 1E is a schematic cross-sectional view along line Z-Z in FIG. 1A, in accordance with the teachings of the present invention; FIG. 2 is a schematic plan view showing the layout of an embodiment of four pixels according to the teachings of the present invention; 3A-3D are schematic diagrams illustrating a portion of a manufacturing process according to an embodiment of the present teachings; fig. 4A is a schematic plan view showing a partial structure of an image sensor according to the teachings of the present invention; FIG. 4B is a schematic cross-sectional view along line X-X in FIG. 4A, in accordance with the teachings of the present invention; FIG. 4C is a schematic enlarged view of portion A in FIG. 4B, according to the teachings of the present invention; FIG. 4D is a schematic cross-sectional view along line Y-Y in FIG. 4A, in accordance with the teachings of the present inventi