CN-122028531-A - CMOS image sensor forming method integrating stress memory technology

Abstract

The invention provides a method for forming a CMOS image sensor integrated with a stress memorization technology. The method comprises the steps of depositing a first oxide layer and a stress medium layer on the surface of a substrate with source and drain injection completed, reserving the stress medium layer of an N-type logic region, removing other regions, removing a residual layer after performing rapid thermal annealing to generate a stress memory effect, depositing a second oxide layer and a nitride layer, reserving a laminated structure of a pixel region through photoetching, and forming metal silicide in the logic region. The invention improves the performance of the logic NMOS device obviously and simultaneously effectively inhibits the dark current of the pixel region by optimizing the stress memory cycle and the self-aligned silicide blocking process, and combines the image quality and the circuit speed.

Inventors

• YU MINGDAO
• GAO LIUCHUN
• OUYANG ZHIHUI
• ZHENG XIAOHUI
• ZHANG DONG
• WANG HAN

Assignees

• 华虹半导体(无锡)有限公司
• 华虹半导体制造(无锡)有限公司

Dates

Publication Date

20260512

Application Date

20260129

Claims (16)

1. 1. A method for forming a CMOS image sensor integrated with stress memorization technology, comprising: Providing a semiconductor substrate, wherein a logic device region and a pixel device region are defined on the semiconductor substrate, the logic device region comprises an N-type logic device region and a P-type logic device region, corresponding grid structures and side wall structures are formed on the N-type logic device region, the P-type logic device region and the pixel device region, and a source-drain region injection process is completed; sequentially depositing a first oxidation layer and a stress medium layer on the surface of the semiconductor substrate, wherein the first oxidation layer and the stress medium layer cover the grid structure and the side wall structure; Step three, performing a photoetching process on the semiconductor substrate to define a stress memory area, wherein in the photoetching process, photoresist above the N-type logic device area is reserved, and photoresist above the P-type logic device area and the pixel device area is removed; Etching to remove the stress medium layer above the P-type logic device region and the pixel device region by taking the photoresist as a mask, and stopping etching on the surface of the first oxide layer; step five, after removing the photoresist, performing a rapid thermal annealing process to activate ion implantation and enable the grid structure of the N-type logic device region to generate a stress memory effect; step six, removing the residual stress medium layer and the first oxide layer; step seven, sequentially depositing a second oxide layer and a second nitride layer on the surface of the semiconductor substrate; Step eight, performing self-aligned silicide blocking layer photoetching and etching processes to define a self-aligned silicide region and a non-self-aligned silicide region, wherein the logic device region is the self-aligned silicide region, and the pixel device region is the non-self-aligned silicide region; and step nine, forming metal silicide in the self-aligned silicide region.
2. 2. The method of claim 1, wherein in the second step, the material of the first oxide layer comprises silicon dioxide.
3. 3. The method of claim 1, wherein in the second step, the stress medium layer comprises silicon nitride having tensile stress.
4. 4. The method of claim 2, wherein in the second step, the first oxide layer has a thickness of 50 to 90 angstroms.
5. 5. The method of claim 3, wherein in the second step, the stress medium layer has a thickness of 250 to 350 angstroms.
6. 6. The method of claim 1, wherein in the second step, the first oxide layer is deposited using ozone-tetraethyl orthosilicate as a precursor.
7. 7. The method of claim 1, further comprising the step of oxygen treating the stress medium layer after the first oxide layer and the stress medium layer are deposited and before the third step.
8. 8. The method of claim 1, wherein in the sixth step, the remaining stress medium layer is removed by wet etching with phosphoric acid trench.
9. 9. The method of claim 1, wherein in step six, a wet etching process using a hydrofluoric acid solution is used to remove the first oxide layer.
10. 10. The method of claim 9, wherein the volume ratio of water to hydrofluoric acid in the hydrofluoric acid solution is 200:1.
11. 11. The method of claim 1, wherein in step seven, the material of the second oxide layer comprises a silicon-rich oxide.
12. 12. The method of claim 1, wherein in step seven, the material of the second nitride layer comprises silicon nitride.
13. 13. The method of claim 11, wherein in the seventh step, the second oxide layer has a thickness of 100 to 150 angstroms.
14. 14. The method of claim 12, wherein in the seventh step, the second nitride layer has a thickness of 240 to 280 angstroms.
15. 15. The method of claim 1, wherein in step seven, the second nitride layer is deposited using a plasma enhanced silicon nitride deposition process.
16. 16. The method of claim 1, wherein in the third step, the N-type logic device region comprises a core NMOS device and an input/output NMOS device, and the P-type logic device region comprises a core PMOS device and an input/output PMOS device.

Description

CMOS image sensor forming method integrating stress memory technology Technical Field The invention relates to the technical field of semiconductors, in particular to a method for forming a CMOS image sensor by integrating a stress memory technology. Background With the continuous development of semiconductor technology, CMOS Image Sensor (CIS) products are widely used due to their low power consumption, high integration, and the like. Currently, two main designs of CIS products are stack design and single chip design. The single chip design scheme integrates the pixel device and the logic circuit device on the same chip, and has the remarkable advantages of small silicon chip consumption, small photomask layer number, low cost, low thermal noise and the like. However, as process nodes evolve to 40nm and below, single chip designs face a serious challenge in terms of how to compromise the high speed performance of logic devices and the optical performance of pixel devices on the same chip. In advanced logic processes, stress Memorization Technology (SMT) is widely used to improve the performance of NMOS devices. According to the technology, the electron mobility of an NMOS channel is improved by a stress transfer mechanism through depositing a high tensile stress film and combining an annealing process, so that the driving current of the device is remarkably improved. However, the conventional SMT technology is directly transplanted into CIS products, which may result in deterioration of pixel performance. For example, laser Spike Annealing (LSA), which is commonly used in conventional logic processes, can further improve logic device performance, but can cause damage to the pixel area due to its instantaneous high temperature characteristics. In addition, if the dielectric layer material in the self-aligned silicide blocking layer (SAB) process is improperly selected, interface state defects or stress mismatch can be introduced, so that dark current of the pixel device is obviously increased, and image quality is seriously affected. In the prior art, a compatible process scheme which can not only effectively improve the performance of a logic NMOS device, but also ensure that the dark current of a pixel device is not deteriorated is lacking. Disclosure of Invention The invention aims to solve the technical problem that the dark current performance of a pixel device is considered while the performance of a logic device is difficult to be improved through the stress memory technology in the existing single-chip CIS product, so that the image quality is reduced. In order to solve the above technical problems, the present invention provides a method for forming a CMOS image sensor integrated with stress memorization technology, comprising the following steps: Providing a semiconductor substrate, wherein a logic device region and a pixel device region are defined on the semiconductor substrate, the logic device region comprises an N-type logic device region and a P-type logic device region, corresponding grid structures and side wall structures are formed on the N-type logic device region, the P-type logic device region and the pixel device region, and a source-drain region injection process is completed; sequentially depositing a first oxidation layer and a stress medium layer on the surface of the semiconductor substrate, wherein the first oxidation layer and the stress medium layer cover the grid structure and the side wall structure; Step three, performing a photoetching process on the semiconductor substrate to define a stress memory area, wherein in the photoetching process, photoresist above the N-type logic device area is reserved, and photoresist above the P-type logic device area and the pixel device area is removed; Etching to remove the stress medium layer above the P-type logic device region and the pixel device region by taking the photoresist as a mask, and stopping etching on the surface of the first oxide layer; step five, after removing the photoresist, performing a rapid thermal annealing process to activate ion implantation and enable the grid structure of the N-type logic device region to generate a stress memory effect; step six, removing the residual stress medium layer and the first oxide layer; step seven, sequentially depositing a second oxide layer and a second nitride layer on the surface of the semiconductor substrate; Step eight, performing self-aligned silicide blocking layer photoetching and etching processes to define a self-aligned silicide region and a non-self-aligned silicide region, wherein the logic device region is the self-aligned silicide region, and the pixel device region is the non-self-aligned silicide region; and step nine, forming metal silicide in the self-aligned silicide region. Preferably, in the second step, the material of the first oxide layer includes silicon dioxide. Preferably, in the second step, the material of the stress medium layer includes silicon