CN-122028561-A - LED chip and preparation method thereof

CN122028561ACN 122028561 ACN122028561 ACN 122028561ACN-122028561-A

Abstract

The application discloses an LED chip and a preparation method thereof, and relates to the technical field of light emitting diodes, wherein the LED chip comprises a bonding substrate, a bonding layer, a specular reflection layer, a dielectric layer and an epitaxial lamination which are laminated on one side of the bonding substrate, wherein a first electrode is arranged on one side of the bonding substrate, which is away from the bonding layer, a second electrode is arranged on one side of the epitaxial lamination, which is away from the bonding substrate, the dielectric layer is provided with a plurality of dielectric holes, the specular reflection layer is filled in the dielectric holes so as to form ohmic contact with a window layer closest to the dielectric layer of the epitaxial lamination, and through arranging the orthographic projection of the dielectric holes on the periphery of the orthographic projection of the second electrode in a plane parallel to the plane of the bonding substrate, the orthographic projection area of the dielectric holes is gradually increased along the orthographic projection direction far from the second electrode, so that current is promoted to expand towards the orthographic projection direction far from the second electrode, namely the edge direction of the chip, and the current distribution is more uniform, and the brightness of the chip is improved.

Inventors

BAN GUOXUN
CAO JINRU
HE PING
LAI YITANG
LI HUANG
ZHANG YI

Assignees

扬州乾照光电有限公司

Dates

Publication Date: 20260512
Application Date: 20260227

Claims (10)

1. An LED chip, comprising: Bonding a substrate; The epitaxial lamination comprises a window layer, a first semiconductor layer, an active layer and a second semiconductor layer which are laminated along the direction deviating from the bonding substrate, wherein the dielectric layer is provided with a plurality of dielectric holes, and the mirror reflection layer is filled in the dielectric holes and forms ohmic contact with the window layer; A first electrode positioned on one side of the bonding substrate away from the bonding layer; and a second electrode on a side of the epitaxial stack facing away from the bond substrate; In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is positioned at the periphery of the orthographic projection of the second electrode, and the orthographic projection area of the dielectric hole is gradually increased along the direction away from the orthographic projection of the second electrode.
2. The LED chip of claim 1, wherein the orthographic projections of the dielectric holes are arranged at least two turns around the orthographic projections of the second electrode in a plane parallel to the plane of the bonding substrate, and the area of the orthographic projections of the dielectric holes in the (i+1) th turn is larger than the area of the orthographic projections of the dielectric holes in the (i) th turn in a direction away from the orthographic projections of the second electrode, i being equal to or larger than 1, and i being an integer.
3. The LED chip of claim 2, wherein the arrangement pattern of the orthographic projections of the dielectric holes for each turn is the same or the arrangement pattern of the orthographic projections of the dielectric holes for at least a part of the turns is different in a plane parallel to the plane of the bonding substrate.
4. The LED chip of claim 2, wherein at least a portion of the dielectric holes are arranged in a circular ring shape or in a polygonal ring shape in a plane parallel to the plane of the bonding substrate.
5. The LED chip of claim 1, wherein the orthographic projections of the dielectric holes are radially arranged with the center of the orthographic projection of the second electrode in a plane parallel to the plane of the bonding substrate, and the area of the orthographic projections of the dielectric holes gradually increases along any arrangement direction away from the orthographic projection of the second electrode.
6. The LED chip of claim 5, wherein the number of orthographic projections of said dielectric holes in a first arrangement direction is greater than the number of orthographic projections of said dielectric holes in a second arrangement direction in a plane parallel to the plane of said bonding substrate, wherein the dimension of said LED chip in said first arrangement direction is greater than the dimension of said LED chip in said second arrangement direction.
7. The LED chip of any of claims 1-6, wherein the orthographic projection of the dielectric holes is circular in shape in a plane parallel to the plane of the bonding substrate, wherein the orthographic projection of the innermost dielectric holes has a radius dimension of not less than 2 μm, the orthographic projection of the outermost dielectric holes has a radius dimension of not more than 5 μm, and the spacing between orthographic projections of the dielectric holes is not less than 5 μm in a direction away from the orthographic projection of the second electrode.
8. The LED chip of any of claims 1-6, wherein the orthographic projection of each of the dielectric holes is at a distance of not less than 15 μm from the orthographic projection of the second electrode and the orthographic projection of each of the dielectric holes is at a distance of not less than 15 μm from the edge of the LED chip in a plane parallel to the plane of the bonding substrate.
9. The LED chip of any of claims 1-6, wherein said dielectric layer comprises a SiO 2 layer or a MgF 2 layer.
10. A method of manufacturing an LED chip, comprising: providing a growth substrate; Forming an epitaxial stack layer on one side of the growth substrate, wherein the epitaxial stack layer comprises a second type semiconductor layer, an active layer, a first type semiconductor layer and a window layer which are stacked along a direction away from the growth substrate; Forming a dielectric layer on one side of the window layer, which is away from the growth substrate, and forming a plurality of dielectric holes in the dielectric layer; forming a mirror reflection layer on one side of the dielectric layer, which is away from the growth substrate, wherein the mirror reflection layer is filled in the dielectric hole and forms ohmic contact with the window layer; Forming a first sub-bonding layer on one side of the specular reflection layer, which is away from the growth substrate; providing a bonding substrate, and forming a second sub-bonding layer on one side of the bonding substrate; Bonding the first sub-bonding layer and the second sub-bonding layer together to form a bonding layer; Removing the growth substrate; Forming a first electrode on one side of the bonding substrate, which is away from the bonding layer, and forming a second electrode on one side of the epitaxial stack, which is away from the bonding substrate; In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is positioned at the periphery of the orthographic projection of the second electrode, and the orthographic projection area of the dielectric hole is gradually increased along the direction away from the orthographic projection of the second electrode.

Description

LED chip and preparation method thereof Technical Field The application relates to the technical field of light emitting diodes, in particular to an LED chip and a preparation method thereof. Background Currently, many Light-Emitting diodes (LEDs) adopt an Omni-directional reflector (Omni-Directional Reflector, ODR) structure to improve the reflection efficiency and further improve the Light extraction efficiency. The omnibearing reflecting mirror structure comprises a semiconductor layer, a dielectric layer and a specular reflecting layer, wherein in order to ensure that the semiconductor layer and the specular reflecting layer form ohmic contact, dielectric holes are formed in the dielectric layer, so that the specular reflecting layer and the semiconductor layer form ohmic contact through the dielectric holes in the filled dielectric layer. However, when the current is applied to the LED chip using the omni-directional reflector, the current distribution is mainly concentrated in the area near the lower part of the top electrode, so that the current distribution is uneven, the current is not easy to spread to the edge of the chip, the current is easy to be crowded, and finally the brightness of the chip is lower. Disclosure of Invention In order to solve the technical problems, the application provides an LED chip and a preparation method thereof, so that current is spread towards the edge of the chip, the current distribution is more uniform, and the brightness of the chip is improved. In order to achieve the above purpose, the present application provides the following technical solutions: in a first aspect, the present application provides an LED chip comprising: Bonding a substrate; The epitaxial lamination comprises a window layer, a first semiconductor layer, an active layer and a second semiconductor layer which are laminated along the direction deviating from the bonding substrate, wherein the dielectric layer is provided with a plurality of dielectric holes, and the mirror reflection layer is filled in the dielectric holes and forms ohmic contact with the window layer; A first electrode positioned on one side of the bonding substrate away from the bonding layer; and a second electrode on a side of the epitaxial stack facing away from the bond substrate; In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is positioned at the periphery of the orthographic projection of the second electrode, and the orthographic projection area of the dielectric hole is gradually increased along the direction away from the orthographic projection of the second electrode. Optionally, in a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole surrounds the orthographic projection of the second electrode for at least two circles, and along a direction far away from the orthographic projection of the second electrode, the area of the orthographic projection of the dielectric hole in the (i+1) th circle is larger than the area of the orthographic projection of the dielectric hole in the (i) th circle, i is more than or equal to 1, and i is an integer. Optionally, in a plane parallel to the plane of the bonding substrate, the arrangement patterns of the orthographic projections of the dielectric holes of each circle are the same, or the arrangement patterns of the orthographic projections of the dielectric holes of at least part of circles are different. Optionally, at least part of the dielectric holes are arranged in a circular ring shape or a polygonal ring shape in a plane parallel to the plane of the bonding substrate. Optionally, in a plane parallel to the plane where the bonding substrate is located, the orthographic projections of the dielectric holes are radially arranged at the center of the orthographic projection of the second electrode, and along any arrangement direction far away from the orthographic projection of the second electrode, the area of the orthographic projections of the dielectric holes is gradually increased. Optionally, in a plane parallel to the plane where the bonding substrate is located, the number of orthographic projections of the dielectric holes along the first arrangement direction is greater than the number of orthographic projections of the dielectric holes along the second arrangement direction, where a size of the LED chip along the first arrangement direction is greater than a size of the LED chip along the second arrangement direction. Optionally, in a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is in a round hole shape, the radius size of the orthographic projection of the innermost dielectric hole is not less than 2 μm, the radius size of the orthographic projection of the outermost dielectric hole is not more than 5 μm, and the interval between the orthographic projections of the dielectric holes is not le