CN-122028649-A - Multi-chip system and expansion method of superconducting quantum chip

CN122028649ACN 122028649 ACN122028649 ACN 122028649ACN-122028649-A

Abstract

The application discloses a multi-chip system and an expansion method of a superconducting quantum chip. The expansion method comprises the steps of preparing an upper sheet with a quantum function layer, preparing a lower sheet with an interconnection wiring layer, performing flip-chip bonding on one upper sheet and one lower sheet to obtain superconducting quantum chip units, and performing off-chip interconnection on a plurality of superconducting quantum chip units to complete expansion of the superconducting quantum chips, wherein the superconducting quantum chip units are superconducting quantum chips with the same or different functions.

Inventors

WANG CHENLU
YANG CHUHONG
CHEN MO
SU TANG
YU HAIFENG

Assignees

北京量子信息科学研究院

Dates

Publication Date: 20260512
Application Date: 20251230

Claims (10)

1. An expansion method of a superconducting quantum chip is characterized by comprising the following steps: preparing an upper sheet with a quantum function layer; preparing a lower sheet with an interconnection wiring layer; Flip-chip bonding is carried out on one upper sheet and one lower sheet to obtain a superconducting quantum chip unit; Carrying out off-chip interconnection on a plurality of superconducting quantum chip units to complete expansion of the superconducting quantum chip; Wherein the superconducting quantum chip units are superconducting quantum chips with the same or different functions.
2. The expansion method of superconducting quantum chip according to claim 1, wherein the preparing the upper sheet having the quantum function layer comprises: and manufacturing superconducting qubits, a resonant cavity and an upper coupling capacitor polar plate on the surface of the first substrate by adopting a standard micro-nano processing technology.
3. The expansion method of the superconducting quantum chip of claim 2, wherein the preparing the lower sheet having the interconnection wiring layer comprises: And manufacturing a local control line, a lower sheet coupling capacitor polar plate, a microwave transmission line, a lead bonding pad and flip-chip bonding bumps on the surface of the second substrate by adopting a standard micro-nano processing technology.
4. The expansion method of superconducting quantum chip of claim 3, wherein flip-chip bonding one of the upper and lower sheets comprises: and aligning and bonding the upper sheet and the lower sheet by using the flip-chip bonding convex points.
5. The expansion method of the superconducting quantum chip of claim 4, wherein interconnecting a plurality of the superconducting quantum chip units comprises: and carrying out bonding encapsulation on the lead bonding pads of the superconducting quantum chips with the same or different functions, and connecting the lead bonding pads with external low-loss microwave conducting wires.
6. The expansion method of superconducting quantum chip of claim 5, wherein one end of the microwave transmission line is connected to the lower coupling capacitor plate, and the other end is connected to the lead pad.
7. The expansion method of superconducting quantum chip according to claim 4, wherein after the flip-chip bonding, a distance between the upper sheet and the lower sheet is 10+ -0.1 μm; The error in the alignment accuracy of the flip-chip bonding was + -0.5 μm.
8. The method of expanding a superconducting quantum chip according to any one of claims 1 to 7, further comprising mounting the superconducting quantum chip completed with the interconnection into a dilution refrigerator.
9. The expansion method of superconducting quantum chip of claim 3, wherein the upper coupling capacitor plate corresponds to the lower coupling capacitor plate in position.
10. A multichip system, characterized in that the interconnection is performed using the expansion method of the superconducting quantum chip according to any one of claims 1-9.

Description

Multi-chip system and expansion method of superconducting quantum chip Technical Field The application relates to the technical field of superconducting quantum computing, in particular to a multi-chip system and an expansion method of a superconducting quantum chip. Background Superconducting quantum computing is one of the most promising technological routes for realizing practical quantum computers. The core is to continuously increase the number of integrated qubits and improve their performance (e.g. coherence time, gate fidelity). However, integrating a large number of qubits on a single chip poses serious challenges of dramatic increases in wiring complexity due to limited chip area, signal crosstalk and loss, high manufacturing process complexity, low yield due to single defects, difficult suppression of electromagnetic crosstalk between densely integrated bits, and difficult heat dissipation management. In order to break through the bottleneck of single-chip integration, a distributed quantum computing scheme is proposed, namely, a quantum processor is decomposed into a plurality of small-scale sub-chips (modules) with relatively independent functions, and then the modules are efficiently interconnected. However, the core bottleneck of this approach is the high performance interconnection between chips. The prior art such as direct wire bonding interconnection or waveguide coupling and the like generally has the problems of large transmission loss, poor signal isolation, limited expansibility, easiness in introducing additional noise and the like. Therefore, developing a chip interconnection method with low loss, high isolation and high expansibility is an urgent need for constructing a large-scale distributed superconducting quantum processor. Disclosure of Invention In order to solve at least one of the above-mentioned shortcomings in the art, the present application is directed to a multi-chip system and an expansion method of a superconducting quantum chip. According to an aspect of the present application, there is provided an expansion method of a superconducting quantum chip, including: preparing an upper sheet with a quantum function layer; preparing a lower sheet with an interconnection wiring layer; Flip-chip bonding is carried out on one upper sheet and one lower sheet to obtain a superconducting quantum chip unit; Carrying out off-chip interconnection on a plurality of superconducting quantum chip units to complete expansion of the superconducting quantum chip; Wherein the superconducting quantum chip units are superconducting quantum chips with the same or different functions. According to some embodiments of the application, preparing a top sheet with a quantum functional layer comprises: and manufacturing superconducting qubits, a resonant cavity and an upper coupling capacitor polar plate on the surface of the first substrate by adopting a standard micro-nano processing technology. According to some embodiments of the application, preparing a lower sheet with an interconnect wiring layer includes: And manufacturing a local control line, a lower sheet coupling capacitor polar plate, a microwave transmission line, a lead bonding pad and flip-chip bonding bumps on the surface of the second substrate by adopting a standard micro-nano processing technology. According to some embodiments of the application, flip-chip bonding the upper and lower sheets comprises: and aligning and bonding the upper sheet and the lower sheet by using the flip-chip bonding convex points. According to some embodiments of the application, interconnecting a plurality of the superconducting quantum chip units comprises: and carrying out bonding encapsulation on the lead bonding pads of the superconducting quantum chips with the same or different functions, and connecting the lead bonding pads with external low-loss microwave conducting wires. According to some embodiments of the application, a microstrip line has one end connected to the lower coupling capacitor plate and the other end connected to the lead pad. According to some embodiments of the application, after the flip chip bonding, a distance between the upper chip and the lower chip is 10±0.1 μm; The alignment accuracy of the flip-chip bonding is + -0.5 μm. According to some embodiments of the application, the method for expanding the superconducting quantum chip further comprises installing the superconducting quantum chip with the interconnected superconducting quantum chip into a dilution refrigerator. According to some embodiments of the application, the upper plate coupling capacitor plate corresponds to the position of the lower plate coupling capacitor plate. According to another aspect of the present application, there is also provided a multi-chip system, which is interconnected by the above-described expansion method of superconducting quantum chips. Drawings Fig. 1 is an internal plan view of a superconducting quantum chip and an interconnect