CN-122028651-A - Method for forming a quantum computing device and a quantum computing device

Abstract

Methods related to processing quantum computing devices to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow subsequent formation of a gate dielectric associated with the device, wherein the selective removal causes a reduction in channel mobility associated with the quantum computing device. The method further includes, prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase channel mobility.

Inventors

• M. C. Cassidy
• S. J. insurance card
• C. N. Allen

Assignees

• 微软技术许可有限责任公司

Dates

Publication Date

20260512

Application Date

20200609

Priority Date

20190816

Claims (20)

1. 1. A topological quantum computing device, comprising: a quantum well formed in the substrate; A superconducting metal layer formed on the surface of the substrate, and A gate dielectric formed over the superconducting metal layer after selectively removing a portion of the superconducting metal layer to define a topologically active region of the topologically quantum computing device, wherein the gate dielectric is formed after subjecting the substrate to a plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase channel mobility of channels adjacent to the quantum well associated with the topologically quantum computing device and to increase a density of electrons within the quantum well, and wherein the plasma treatment further causes a clean semiconductor-dielectric interface to be formed between the topologically active region of the topologically quantum computing device and a topologically inactive region of the topologically quantum computing device.
2. 2. The quantum computing device of claim 1, wherein the set of parameters includes a parameter of any precursor associated with the plasma process, a density of any ion or electron associated with the plasma process, or a type of power source associated with the plasma process.
3. 3. The quantum computing device of claim 2, wherein the precursors associated with the plasma treatment comprise argon and hydrogen.
4. 4. The quantum computing device of claim 1, wherein the plasma processing comprises remote plasma processing.
5. 5. The quantum computing device of claim 4, wherein the remote plasma processing is provided using a power source selected from the group consisting of a direct current DC power source, a pulsed-direct current power source, or a radio frequency RF power source.
6. 6. The quantum computing device of claim 1, wherein the quantum computing device comprises at least one of a two-dimensional electron gas 2DEG, a gas-liquid-solid VLS nanowire, or a structure formed using selective region growth.
7. 7. A topological quantum computing device, comprising: A topologically active region formed in the substrate by selectively removing a portion of the superconducting metal layer formed over the semiconductor layer, wherein the portion of the superconducting metal layer is removed to expose a portion of the semiconductor layer to form an exposed portion, and A gate formed over the exposed portion of the semiconductor layer, wherein the gate comprises a gate dielectric formed over at least the exposed portion of the semiconductor layer, wherein the gate dielectric is formed after subjecting the substrate to a plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase channel mobility of channels adjacent to the topologically active region and to increase a density of electrons within the topologically active region, and wherein the plasma treatment further causes a clean semiconductor-dielectric interface to be formed between the topologically active region of the topologically quantum computing device and a topologically inactive region of the topologically quantum computing device.
8. 8. The quantum computing device of claim 7, wherein the gate is configured to control an operational aspect associated with the quantum computing device.
9. 9. The quantum computing device of claim 7, wherein the topologically active region comprises a quantum well.
10. 10. The quantum computing device of claim 7, wherein the quantum computing device comprises at least one of a two-dimensional electron gas 2DEG, a gas-liquid-solid VLS nanowire, or a structure formed using selective region growth.
11. 11. The quantum computing device of claim 7, wherein the set of parameters includes a parameter of any precursor associated with the plasma process, a density of any ion or electron associated with the plasma process, or a type of power source associated with the plasma process.
12. 12. The quantum computing device of claim 11, wherein the precursors associated with the plasma treatment comprise argon and hydrogen.
13. 13. The quantum computing device of claim 11, wherein the plasma processing comprises remote plasma processing.
14. 14. The quantum computing device of claim 13, wherein the remote plasma processing is provided using a power source selected from the group consisting of a direct current DC power source, a pulsed-direct current power source, or a radio frequency RF power source.
15. 15. A topological quantum computing device, comprising: A quantum well formed in a substrate by selectively removing a portion of a superconducting metal layer formed over a semiconductor layer, wherein the portion of the superconducting metal layer is removed to expose a portion of the semiconductor layer to form an exposed portion, and A gate formed over the exposed portion of the semiconductor layer, wherein the gate comprises a gate dielectric formed over at least the exposed portion of the semiconductor layer, wherein the gate dielectric is formed after subjecting the substrate to a plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase channel mobility of a channel adjacent to the quantum well and to increase a density of electrons within the quantum well, and wherein the plasma treatment further causes a clean semiconductor-dielectric interface to be formed between the quantum well and a topologically inactive region of the topologic quantum computing device.
16. 16. The quantum computing device of claim 15, wherein the gate is configured to control an operational aspect associated with the quantum computing device.
17. 17. The quantum computing device of claim 15, wherein the set of parameters includes a parameter of any precursor associated with the plasma process, a density of any ion or electron associated with the plasma process, or a type of power source associated with the plasma process.
18. 18. The quantum computing device of claim 17, wherein the precursors associated with the plasma treatment comprise argon and hydrogen.
19. 19. The quantum computing device of claim 15, wherein the substrate comprises one or more of indium phosphide InP, indium arsenide InAs, indium antimonide InSb, or cadmium mercury telluride HgCdTe.
20. 20. The quantum computing device of claim 15, wherein the superconducting metal layer comprises one of aluminum or niobium.

Description

Method for forming a quantum computing device and a quantum computing device Background Various physical systems have been proposed for constructing quantum computers, including trapping ions, nuclear spins, electron spins in semiconductors, photons, and other types of systems. Each of these systems is intended to implement a qubit (quantum equivalent of a bit) that is not of value 0 or value 1, but is represented by a two-dimensional vector evolving according to quantum physics rules. Topological quantum computing may provide better performance than traditional quantum computing methods. Disclosure of Invention In one example, the present disclosure relates to a method for forming a quantum computing device. The method may include forming a superconducting metal layer on a surface of the wafer. The method may further include selectively removing a portion of the superconducting metal layer to allow for subsequent formation of a gate dielectric associated with the device, wherein the selective removal causes a reduction in channel mobility associated with the quantum computing device. The method may further include subjecting the wafer to a plasma treatment prior to forming the gate dielectric, wherein a set of parameters associated with the plasma treatment is selected to increase channel mobility. In another aspect, the present disclosure is directed to a quantum computing device including a quantum well formed in a substrate. The quantum computing device may further include a superconducting metal layer formed on a surface of the substrate. The quantum computing device may further include a gate dielectric associated with the quantum computing device, the gate dielectric formed after selectively removing a portion of the superconducting metal layer, wherein the selective removal causes a reduction in channel mobility adjacent to a quantum well formed in the substrate, and wherein the gate dielectric is formed after subjecting the substrate to a plasma treatment, wherein a parameter set associated with the plasma treatment is selected to increase channel mobility adjacent to the quantum well. In yet another aspect, the present disclosure is directed to a method for processing a wafer including quantum wells to form a quantum computing device. The method may include forming a superconducting metal layer on a surface of the wafer. The method may further include selectively removing a portion of the superconducting metal layer to allow subsequent formation of a gate dielectric associated with the quantum computing device, wherein the selective removal causes a reduction in channel mobility adjacent to the quantum well. The method may further include, prior to forming the gate dielectric, subjecting the wafer to an in situ plasma treatment utilizing at least hydrogen as a precursor associated with the plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase channel mobility adjacent to the quantum well such that channel mobility adjacent to the quantum well and intrinsic channel mobility are substantially the same. This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Drawings The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 illustrates a cross-sectional view of an example topological quantum computing device during at least one step for forming the device; FIG. 2 illustrates a cross-sectional view of an example topological quantum computing device during at least one step for forming the device; FIG. 3 illustrates a cross-sectional view of an example topological quantum computing device during at least one step for forming the device; FIG. 4 illustrates a graphical representation of damage to a semiconductor adjacent to a quantum well, according to one example; FIG. 5 shows a plot of mobility versus density for a test sample; FIG. 6 illustrates peak mobility for various processing implementations; FIG. 7 shows peak mobility versus density at zero gate voltage for various processes; FIG. 8 shows a graphical representation of a change in semiconductor caused by plasma processing; FIG. 9 illustrates a cross-sectional view of an example topological quantum computing device during at least one step for forming the device; FIG. 10 illustrates a cross-sectional view of an example topological quantum computing device during at least one step for forming the device; FIG. 11 illustrates a top view of an example topological quantum computing device during at least one step f