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CN-122028667-A - Wafer dicing method and related device

CN122028667ACN 122028667 ACN122028667 ACN 122028667ACN-122028667-A

Abstract

The application discloses a wafer dicing method and device, and belongs to the field of superconducting quantum chip manufacturing. The wafer dicing method comprises the steps of establishing a structural model of a wafer, simulating the structural model to obtain a stress threshold value when the wafer is broken, and controlling the load applied to the wafer by a dicing saw according to the stress threshold value so as to cut the wafer. Dicing a wafer using the above method can significantly reduce the risk of die chipping.

Inventors

  • ZHAO YONGJIE

Assignees

  • 本源天工(郑州)量子科技有限公司

Dates

Publication Date
20260512
Application Date
20241101

Claims (10)

  1. 1. A wafer dicing method, comprising: establishing a structural model of the wafer; Simulating the structural model to obtain a stress threshold value when the wafer is cracked; And controlling the load applied to the wafer by the dicing saw according to the stress threshold value so as to cut the wafer.
  2. 2. The wafer dicing method of claim 1, wherein after obtaining the stress threshold at which the wafer is broken, the dicing method further comprises detecting the thickness of the wafer before controlling the load applied to the wafer by the dicing machine to dice the wafer according to the stress threshold; Controlling the load applied to the wafer by the dicing saw according to the stress threshold comprises adjusting the amount of the dicing mechanism of the dicing saw to be cut relative to the wafer according to the thickness, so that the load applied to the wafer is smaller than the stress threshold.
  3. 3. The wafer dicing method according to claim 2, wherein in detecting the thickness of the wafer, it is also detected whether the wafer is of a type defined by flip chip; controlling the load applied to the wafer by the dicing saw according to the stress threshold value comprises adjusting the cutter setting amount of a dicing mechanism of the dicing saw according to the thickness and the type of the wafer, so that the load applied to the wafer is smaller than the stress threshold value.
  4. 4. The wafer dicing method according to claim 1, wherein after obtaining the stress threshold value at which the wafer is broken, the dicing method further comprises detecting dicing lanes corresponding to dicing lanes to which the dicing machine performs dicing to apply a load before controlling the load applied to the wafer by the dicing machine to dice the wafer according to the stress threshold value; and planning a correction amount of the load according to the wafer shape at the track of the scribe lane.
  5. 5. The wafer dicing method according to claim 1, wherein the applied load is constant when dicing is performed in any dicing lane of the wafer.
  6. 6. The wafer dicing method according to claim 1, the dicing method is characterized by further comprising the following steps: And in the dicing process, cleaning the surface of the cutter blade of the dicing saw after every preset time.
  7. 7. The wafer dicing method according to claim 1, wherein a protective film is attached to a surface of the diced wafer.
  8. 8. A wafer dicing apparatus, comprising: The model creation module is used for creating a structural model of the wafer; the simulation module is used for simulating the structural model to obtain a stress threshold value when the wafer is cracked; And the cutting module is used for controlling the load applied to the wafer by the dicing saw according to the stress threshold value so as to cut the wafer.
  9. 9. An electronic device is characterized by comprising a processor and a memory; The processor is connected to a memory, wherein the memory is configured to store a computer program, and the processor is configured to invoke the computer program to perform the wafer dicing method according to any of claims 1-7.
  10. 10. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed by a processor, perform the wafer dicing method according to any one of claims 1-6.

Description

Wafer dicing method and related device Technical Field The application belongs to the field of quantum information, in particular to the field of superconducting quantum chip manufacturing, and particularly relates to a wafer dicing method and a related device. Background The wafer is prepared after the previous process, and the chips on the wafer are separated by cutting and then packaged. The wafer dicing process is also different depending on the thickness: wafers with a thickness of 100 μm or more are generally cut using a blade; A wafer having a thickness of 30 to 100 μm is generally cut using a laser; A wafer with a thickness less than 30 μm is cut by using plasma; the dicing process therein may also be described simply as dicing. Dicing is the last ring in the integrated circuit manufacturing process, and is a process of dicing a wafer from a whole wafer to a single chip after finishing processing and manufacturing, and is an indispensable process for wafer dicing, whether a traditional chip package or an advanced wafer level packaging technology. Wafer dicing can be divided into dicing (e.g., dicing hidden in laser dicing) and dicing. After the wafer is processed and manufactured, a scribing channel is reserved on the wafer. First, a wafer is stuck to a protective film, and a laser is used to make a invisible cut. The hidden cutting can break the internal structure of the silicon in the scribing channel area, then the wafer is expanded by a wafer expander to form a single chip, and finally the tackiness of the protective film is relieved by a glue releaser, so that the chip is taken down. However, in the dicing process, the chip is prone to cracking, and the like, and particularly the problem described above becomes more serious when there is a through-silicon via in the chip. Disclosure of Invention Examples of the present application provide a wafer dicing method and related apparatus for dicing a wafer to obtain individual chips. The method can realize effective control of the load applied to the wafer in the dicing process so as to reduce the risk of cracking of the wafer in the dicing process. The exemplary embodiment of the present application is implemented as follows. In a first aspect, the application discloses a wafer dicing method, comprising: establishing a structural model of the wafer; simulating the structural model to obtain a stress threshold value when the wafer is cracked; and controlling the load applied to the wafer by the dicing saw according to the stress threshold value so as to cut the wafer. According to some examples of the application, after obtaining the stress threshold when the wafer breaks, the dicing method further comprises detecting the thickness of the wafer before controlling the load applied to the wafer by the dicing saw to dice the wafer according to the stress threshold; Controlling the load applied to the wafer by the dicing saw according to the stress threshold includes adjusting the amount of the dicing mechanism of the dicing saw to the wafer according to the thickness such that the load applied to the wafer is less than the stress threshold. In accordance with some examples of this application, in detecting the thickness of the wafer, it is also detected whether the wafer is of the type defined by flip chip; Controlling the load applied to the wafer by the dicing saw according to the stress threshold comprises adjusting the amount of the lower cutter of the dicing mechanism of the dicing saw according to the thickness and the type of the wafer, so that the load applied to the wafer is smaller than the stress threshold. According to some examples of the application, after obtaining the stress threshold when the wafer breaks, the dicing method further comprises detecting dicing lanes corresponding to the dicing lanes applied by the dicing machine to cut the wafer before controlling the load applied by the dicing machine to the wafer according to the stress threshold to cut the wafer; and planning a correction amount of the load according to the wafer shape at the track of the scribe lane. According to some examples of the application, the applied load is constant while dicing in any scribe lane of the wafer. According to some examples of the application, the dicing method further comprises: And in the dicing process, cleaning the surface of the cutter blade of the dicing saw after every preset time. According to some examples of the application, the cut wafer surface is adhered with a protective film. In a second aspect, the present application discloses a wafer dicing apparatus comprising: The model creation module is used for creating a structural model of the wafer; The simulation module is used for simulating the structural model to obtain a stress threshold value when the wafer is cracked; and the cutting module is used for controlling the load applied to the wafer by the dicing saw according to the stress threshold value so as to cut the wafer. In a