CN-122028668-A - Wafer cutting method

Abstract

The application discloses a wafer cutting method which comprises the following steps of forming a protective layer on the front surface of a wafer, removing a part of the protective layer corresponding to a scribing channel of the wafer to expose the scribing channel, performing physical cutting on the scribing channel at the edge of the wafer along a cleavage surface inherent to the wafer, wherein the size of the physical cutting is far smaller than the diameter of the wafer, performing cleavage along the scribing channel to cut the wafer into a plurality of chips, and removing the protective layer to obtain the cut chips.

Inventors

• Qin Fengyou
• ZHAO HUI
• NIE HUI

Assignees

• 英伟芯(上海)科技有限公司

Dates

Publication Date

20260512

Application Date

20260225

Claims (9)

1. 1. A wafer dicing method, comprising the steps of: forming a protective layer on the front surface of the wafer; removing the part of the protective layer corresponding to the scribing channel of the wafer to expose the scribing channel; Performing physical dicing along a cleavage plane inherent to the wafer on scribe lanes at the edge of the wafer, the physical dicing being of a size substantially less than the diameter of the wafer; cleaving along the scribe lanes, and cutting the wafer into a plurality of chips; and removing the protective layer to obtain the cut chip.
2. 2. The method of claim 1, wherein the material of the wafer comprises gallium arsenide, indium phosphide, or zinc sulfide.
3. 3. The wafer dicing method according to claim 1, wherein the thickness of the wafer is 100 μm to 800 μm, and the diameter of the wafer is 2 inches or more.
4. 4. The method according to claim 1, wherein the material of the protective layer is an organic material or an inorganic material, and the thickness of the protective layer is 0.1 μm to 10 μm.
5. 5. The method of claim 1, wherein the scribe line has an etched trench.
6. 6. The method of claim 5, wherein the etched groove is a V-groove or a U-groove.
7. 7. The method of claim 1, wherein the scribe line has a width of between 10 μm and 500 μm.
8. 8. The wafer dicing method of claim 1, wherein the physical dicing is between 1 μm and 1mm in size.
9. 9. The method of claim 1, wherein the removing the portion of the protective layer corresponding to the scribe line of the wafer is performed by developing and/or etching the protective layer.

Description

Wafer cutting method Technical Field The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer cutting method. Background The dicing of chips is a key step in the semiconductor manufacturing process, and is performed by dividing the whole wafer into individual chip units, so that the subsequent processes such as bonding, packaging, etc. can be performed, and the process directly affects the yield, reliability and production cost of the chips. At present, wafer cutting modes mainly comprise mechanical cutting, laser cutting, plasma cutting, cleavage cutting and the like. Mechanical dicing uses a diamond blade for dicing and breaking, although at a lower cost, mechanical stresses and microcracks are easily generated in the dicing streets, which may lead to chip edge damage or hidden breakage for brittle materials. The laser cutting has the advantages of non-contact and high precision by locally heating and removing materials through a high-energy laser beam, but when processing low-melting-point, low-thermal-conductivity or easily-decomposed semiconductor materials, such as gallium arsenide (GaAs) or indium phosphide (InP) and the like, slag formed by melting and resolidifying the materials can be attached to the side wall of a cutting channel and the surface of a chip, so that pollution which is difficult to remove is introduced, and the subsequent packaging process or device performance is influenced. Cleavage dicing is a unique process for the above-described materials having a distinct cleavage plane, such as group III-V compound semiconductors. The method utilizes the inherent cleavage surface of the crystal, and breaks the wafer along a specific crystal direction by applying mechanical stress, so that a smooth separation surface like a mirror is obtained, and the pollution of a heat affected zone and slag caused by laser processing can be avoided theoretically. However, the cleaving cutting process has significant drawbacks in practical applications, firstly, in that during cleaving breaking, the edges of the fracture are prone to generate micro-or sub-micro-scale chips that splash and contaminate adjacent chip functional areas, and secondly, the process requires that the cutting direction must be precisely aligned with the inherent cleavage plane of the crystal, any minor misalignment can lead to rough fracture planes, particulate generation, and even the initiation of uncontrolled cracking, causing chip damage. Thus, while cleavage cuts have unique advantages over certain materials, their inherent contamination risks and stringent process control requirements limit their wide range of applications and further improvement in yield. In view of the foregoing, there is no wafer dicing solution available in the prior art that is suitable for semiconductor materials that are prone to slag or chip contamination, while ensuring both high cleanliness and high process tolerances. Disclosure of Invention The application provides a wafer cutting method, which is characterized in that an isolation protective layer is formed on the front surface of a wafer before cleavage cutting, and micron-sized physical cutting is carried out only on an edge scribing channel, so that the pollution of cleavage scraps to a chip area is effectively prevented, and meanwhile, a deviation tolerance is provided for cleavage alignment, so that the cutting cleanliness and the process yield are remarkably improved. At the same time, the protective layer reduces the risk of breakage of the intrinsic cleavage plane of the functional region crystal caused by wafer substrate defects. The application discloses a wafer cutting method which comprises the following steps of forming a protective layer on the front surface of a wafer, removing a part of the protective layer corresponding to a scribing channel of the wafer to expose the scribing channel, performing physical cutting on the scribing channel at the edge of the wafer along a cleavage surface inherent to the wafer, wherein the size of the physical cutting is far smaller than the diameter of the wafer, performing cleavage along the scribing channel to cut the wafer into a plurality of chips, and removing the protective layer to obtain the cut chips. According to the wafer cutting method, the chip area is fully covered and isolated through the protective layer, and only the scribing channel area is exposed, so that scraps generated in the cleavage process are physically blocked outside the chip functional area, and meanwhile, the wafer edge is subjected to physical cutting with extremely small size, so that pollution caused by large-area mechanical contact is avoided, and double improvement of cutting cleanliness and process tolerance is realized. In the wafer cutting method disclosed by the application, the material of the wafer comprises gallium arsenide, indium phosphide or zinc sulfide. According to the wafer cutting method, for compound semi