CN-122028675-A - Etching system and etching method

Abstract

The present disclosure provides an etching system. The etching system includes a process chamber, an image and temperature control element, and an artificial intelligence control module. The process chamber is configured to perform an etching process on a first wafer according to a first etching recipe. The image and temperature control element is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image meets a predetermined requirement. When the thermal image does not meet the predetermined requirement, the artificial intelligence control module is configured to update the first etching recipe according to a plurality of parameters to generate a second etching recipe.

Inventors

• HUANG ZEYAO

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260512

Application Date

20250421

Priority Date

20241101

Claims (20)

1. 1. An etching system, comprising: A process chamber configured to perform an etching process on a first wafer according to a first etching recipe; an image and temperature control element configured to generate a thermal image of the first wafer during the etching process, and An artificial intelligence control module configured to determine whether the thermal image meets a predetermined requirement, wherein when the thermal image does not meet the predetermined requirement, the artificial intelligence control module is configured to update the first etching recipe according to a plurality of parameters to generate a second etching recipe.
2. 2. The etching system of claim 1, wherein the artificial intelligence control module is integrated within the process chamber.
3. 3. The etching system of claim 1, wherein the process chamber comprises: an electrostatic chuck configured to attach the first wafer by an electro-adhesion; A plurality of thermal sensors configured to sense a plurality of temperature information of the first wafer, respectively, and A base configured to support the electrostatic chuck.
4. 4. The etching system of claim 3, wherein the pedestal comprises: a passage configured to transport a heat transfer liquid to control a temperature of the first wafer.
5. 5. The etching system of claim 4, wherein a flow rate of the heat transfer liquid is monitored in real time and transmitted to the artificial intelligence control module, wherein the artificial intelligence control module updates the first etching recipe based on the flow rate to generate the second etching recipe when the thermal image does not meet the predetermined requirement.
6. 6. The etching system of claim 5, wherein the artificial intelligence control module is further configured to update the flow rate based on the thermal image when the artificial intelligence control module updates the first etching recipe.
7. 7. The etching system of claim 3, wherein an air gap exists between the first wafer and the electrostatic chuck when the electrostatic chuck is attached to the first wafer, wherein a heat transfer gas is purged into the air gap, a purge pressure of the heat transfer gas is monitored centrally and in real time, and the purge pressure is transmitted to the artificial intelligence control module.
8. 8. The etching system of claim 7, wherein the artificial intelligence control module updates the first etching recipe based on the purge pressure when the thermal image does not meet the predetermined requirement.
9. 9. The etching system of claim 8, wherein the artificial intelligence control module is further configured to update the purge pressure based on the thermal image when the artificial intelligence control module updates the first etching recipe.
10. 10. The etching system of claim 3, wherein the image and temperature control element is configured to obtain the plurality of temperature information to generate the thermal image.
11. 11. The etching system of claim 3, wherein the plurality of temperature information indicates a temperature of a plurality of regions of the first wafer, respectively.
12. 12. The etching system of claim 3, wherein the electrostatic chuck comprises: A dielectric; an electrode buried in the dielectric body, and A voltage supply configured to provide a voltage to the electrode, Wherein, due to the voltage, a first charge is accumulated on the electrode, and a second charge is induced by the first charge and accumulated on the first wafer.
13. 13. The etching system of claim 3, wherein the electrostatic chuck comprises: A dielectric; a first electrode buried in the dielectric; A second electrode buried in the dielectric body and separated from the first electrode, and A voltage supply coupled between the first electrode and the second electrode and configured to provide a voltage between the first electrode and the second electrode, Wherein, due to the voltage, a first positive charge and a first negative charge are accumulated on the first electrode and the second electrode, respectively, Wherein a second negative charge is induced and accumulated on one portion of the first wafer by the first positive charge and a second positive charge is induced and accumulated on another portion of the first wafer by the first negative charge.
14. 14. The etching system of claim 1, further comprising: a measurement element configured to monitor the plurality of parameters of the etching process and to communicate the plurality of parameters to the artificial intelligence control module.
15. 15. The etching system of claim 1, wherein the process chamber is further configured to perform the etching process on a second wafer according to the second etching recipe, wherein the second etching recipe is different from the first etching recipe.
16. 16. An etching method, comprising: Obtaining a thermal image of a first wafer; performing an etching process on the first wafer according to a first etching recipe; judging whether the thermal image meets a preset requirement or not through an artificial intelligent control module; when the thermal image does not meet the predetermined requirement, the artificial intelligence control module updates the first etching recipe according to the thermal image to generate a second etching recipe, and An etching process is performed on a second wafer according to the second etching recipe.
17. 17. The etching method of claim 16, wherein performing the etching process on the first wafer according to the first etching recipe comprises: Respectively sensing a plurality of temperature information of a plurality of areas of the first wafer; generating a plasma to etch the first wafer; Purging a heat transfer gas to control a temperature of the first wafer, and A heat transfer liquid is transferred to control the temperature of the first wafer.
18. 18. The etching method of claim 17, further comprising: monitoring a flow rate of the heat transfer liquid and a purge pressure of the heat transfer gas in real time, and And updating the flow and the purge pressure by the artificial intelligence control module when the thermal image does not meet the predetermined requirement.
19. 19. The etching method of claim 18, wherein the heat transfer gas is purged with the updated purge pressure and the heat transfer liquid is transferred with the updated flow rate when the etching process is performed on the second wafer according to the second etching recipe.
20. 20. The etching method of claim 17, wherein sensing the plurality of temperature information is performed while the plasma is not being generated.

Description

Etching system and etching method Technical Field The present application claims priority from U.S. patent application Ser. No. 18/934,443 (i.e., priority date "day 11 of 2024"), the contents of which are incorporated herein by reference in their entirety. The present disclosure relates to an etching system and an etching method. In particular, to an etching system and an etching method using an artificial intelligent control module. Background Semiconductor devices are used in various electronic applications such as personal computers, cell phones, digital cameras, or other electronic devices. The size of the semiconductor device is gradually reduced to meet the increasing demand of computing power. However, during the process of downsizing, various problems are added, and such problems continue to increase. In addition, temperature variations can also cause the risk of wafer breakage, especially for thinner wafers or wafers subjected to scaling processes. Thus, challenges continue to be addressed in achieving improved quality, yield, performance and reliability, and reduced complexity. The foregoing description of "prior art" merely provides background, and is not admitted to disclose the subject matter of the present disclosure, do not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure. Disclosure of Invention An embodiment of the present disclosure provides an etching system. The etching system includes a process chamber, an image and temperature control element, and an artificial intelligence control module. The process chamber is configured to perform an etching process on a first wafer according to a first etching recipe. The image and temperature control element is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image meets a predetermined requirement. When the thermal image does not meet the predetermined requirement, the artificial intelligence control module is configured to update the first etching recipe according to a plurality of parameters to generate a second etching recipe. Another embodiment of the present disclosure provides an etching method. The etching method comprises the steps of obtaining a thermal image of a first wafer, executing an etching process on the first wafer according to a first etching formula, judging whether the thermal image meets a preset requirement or not by means of an artificial intelligent control module, updating the first etching formula according to the thermal image to generate a second etching formula when the thermal image does not meet the preset requirement, and executing the etching process on a second wafer according to the second etching formula. By adopting the artificial intelligent control module, the temperature of the wafer can be controlled more accurately and more timely. Therefore, the yield and/or reliability of the wafer can be improved. The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure are described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. Drawings Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It will be appreciated that the various features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1 is a schematic diagram illustrating an etching system in accordance with some embodiments of the present disclosure. FIG. 2 is a schematic diagram illustrating a process chamber according to some embodiments of the present disclosure. Fig. 3 is a schematic diagram illustrating the electrical attraction of some embodiments of the present disclosure between a wafer and an electrostatic chuck. FIG. 4 is a schematic diagram illustrating a process chamber according to other embodiments of the present disclosure. Fig. 5 is a schematic diagram illustrating the electrical attraction between a wafer and an electrostatic chuck according to other embodiments of the present disclosure. Fig. 6 and 7 are schematic structural diagrams illustrating the electrical attraction betwee