CN-122028701-A - Bonding test structure and test method

CN122028701ACN 122028701 ACN122028701 ACN 122028701ACN-122028701-A

Abstract

The invention relates to the technical field of semiconductor testing, in particular to a bonding test structure and a bonding test method, wherein the bonding test structure comprises a first semiconductor structure, a second semiconductor structure and a first bonding surface, wherein the first semiconductor structure is provided with a plurality of mutually separated first conductive parts, and the first conductive parts are exposed to the first bonding surface of the first semiconductor structure; the second semiconductor structure is connected with the first semiconductor structure in a bonding way, the second semiconductor structure is provided with a second bonding surface, the second bonding surface is bonded with the first bonding surface, the second semiconductor structure is internally provided with a second conductive part which is exposed to the second bonding surface, and when the second semiconductor structure and the first semiconductor structure are in standard bonding positions, at least part of the surface of the second conductive part is in dislocation contact with at least part of the surface of the first conductive part, so that the hybrid bonding precision of the whole wafer can be quickly and effectively monitored.

Inventors

CAO RUIXIA
LIU WEI
PAN CHAO
CHENG CUI

Assignees

湖北三维半导体集成创新中心有限责任公司

Dates

Publication Date: 20260512
Application Date: 20241105

Claims (10)

1. A bond test structure, comprising: the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a first bonding surface, wherein the first semiconductor structure is provided with a plurality of mutually separated first conductive parts, and the first conductive parts are exposed to the first bonding surface of the first semiconductor structure; A second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure having a second bonding surface bonded to the first bonding surface, the second semiconductor structure having a second conductive portion therein, the second conductive portion being exposed to the second bonding surface; when the second semiconductor structure and the first semiconductor structure are in standard bonding positions, at least part of the surface of the second conductive part is in dislocation contact with at least part of the surface of the first conductive part; Two mutually separated test pads are positioned in the first semiconductor structure, and when the second semiconductor structure and the first semiconductor structure are in standard bonding positions, the two test pads are electrically connected through the first conductive part and the second conductive part.
2. The bonding test structure of claim 1, wherein the first conductive portion comprises a first bonding layer and a first interconnect layer within the first semiconductor structure, the first bonding surface exposing the first bonding layer, the first interconnect layer electrically connecting the first bonding layer with a corresponding test pad; The second conductive portion includes a second bonding layer and a second interconnect layer within the second semiconductor structure that are discrete from each other, the second bonding surface exposing the second bonding layer, the second interconnect layer electrically connecting the second bonding layers.
3. The bond test structure of claim 2, wherein the first semiconductor structure further comprises a first substrate and a first insulating layer on the first substrate, the first insulating layer covering the first interconnect layer and the first substrate, the first insulating layer having a first opening therein exposing the first interconnect layer, the first bond layer disposed in the first opening; The second semiconductor structure further comprises a second substrate and a second insulating layer, the second interconnection layer is located on the second substrate, the second insulating layer covers the second interconnection layer and the second substrate, a second opening is formed in the second insulating layer, the second opening exposes the second interconnection layer, and the second bonding layer is arranged in the second opening.
4. The bond test structure of claim 2, comprising: the second bonding layer is provided with a first projection projected on the second bonding surface; The second interconnect layer has a second projection that projects on the second bonding surface; The first projection is arranged in a central symmetry mode based on the second projection.
5. The bond test structure of claim 4, comprising: The first bonding layer is provided with a third projection projected on the second bonding surface; When the second semiconductor structure and the first semiconductor structure are in standard bonding positions, the first projection and the third projection are provided with overlapping areas, and the overlapping areas are arranged in a central symmetry mode based on the second projection.
6. The bonding test structure according to claim 5, wherein the dimensions of the overlap regions corresponding to different ones of the test pads are different.
7. The bond testing structure of claim 5 or 6, wherein the shape of the first projection and the shape of the third projection are the same, and wherein the size of the first projection and the size of the third projection are the same.
8. The bonding test structure of any of claims 7, wherein the overlapping regions on both sides of the second projection are identical in shape and identical in size when the second semiconductor structure and the first semiconductor structure are in a standard bonding position.
9. A method of testing, comprising: providing a plurality of bonding test structures according to any one of claims 1-8; Performing an electrical test on the bonding test structure to obtain electrical parameters of a test pad in the bonding test structure; and judging whether the bonding test structure corresponds to the semiconductor structure to be aligned or not based on the electrical parameters of the test pads.
10. The test method according to claim 9, comprising: the number of the bonding test structures is multiple, and the sizes of the overlapping areas corresponding to the test pads in different bonding test structures are different; the testing method further comprises the step of obtaining the alignment precision of the bonding testing structure corresponding to the semiconductor structure based on the electrical parameters of different testing pads.

Description

Bonding test structure and test method Technical Field The disclosure relates to the technical field of semiconductor testing, in particular to a bonding test structure and a bonding test method. Background Compared with the traditional bonding technology, the hybrid bonding technology can realize the advantages of high-density interconnection, low resistance delay, good heat dissipation performance, miniaturized high-performance packaging and the like, and is one of important technologies in the field of semiconductor packaging. Bonding alignment accuracy is a key factor affecting bonding quality, and currently, in the semiconductor manufacturing process, nested alignment points (mark) are commonly measured to obtain alignment accuracy (overlay), but the method is generally limited by the number of alignment points and the number of measurement points on a whole wafer, and the measurement result cannot completely reflect hybrid bonding alignment quality on the whole wafer; in addition, after all the processing processes of the wafer are completed, CP (Chip Probing) of the wafer needs to be tested, and CP test can also monitor alignment accuracy (overlay) of all chips (chips), however, CP test takes longer time, and CP test is often used in a product packaging stage, and problems are found later. Disclosure of Invention The present disclosure provides a bonding test structure and a test method, which can rapidly and effectively monitor hybrid bonding precision of a whole wafer through testing the bonding test structure in a wafer acceptance test stage (WAFER ACCEPTANCE TEST, WAT). In a first aspect, the present disclosure provides a bonding test structure, including a first semiconductor structure having a first bonding surface, a first semiconductor structure having a plurality of first conductive portions therein, the first conductive portions being exposed to the first bonding surface of the first semiconductor structure, a second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure having a second bonding surface, the second bonding surface being bonded to the first bonding surface, the second semiconductor structure having a second conductive portion therein, the second conductive portion being exposed to the second bonding surface, at least a portion of a surface of the second conductive portion being in dislocated contact with at least a portion of the surface of the first conductive portion when the second semiconductor structure and the first semiconductor structure are in a standard bonding position, and two mutually discrete test pads within the first semiconductor structure, the two test pads being electrically connected through the first conductive portions and the second conductive portions when the second semiconductor structure and the first semiconductor structure are in the standard bonding position. In some embodiments, the first conductive portion includes a first bonding layer and a first interconnect layer within the first semiconductor structure, the first bonding surface exposing the first bonding layer, the first interconnect layer electrically connecting the first bonding layer to a corresponding test pad, and the second conductive portion includes a second bonding layer and a second interconnect layer within the second semiconductor structure that are separate from each other, the second bonding surface exposing the second bonding layer, the second interconnect layer electrically connecting the second bonding layers. In some embodiments, the first semiconductor structure further includes a first substrate and a first insulating layer, the first insulating layer is located on the first substrate, the first insulating layer covers the first interconnect layer and the first substrate, the first insulating layer has a first opening therein, the first opening exposes the first interconnect layer, the first bonding layer is disposed in the first opening, the second semiconductor structure further includes a second substrate and a second insulating layer, the second interconnect layer is located on the second substrate, the second insulating layer covers the second interconnect layer and the second substrate, the second insulating layer has a second opening therein, the second opening exposes the second interconnect layer, and the second bonding layer is disposed in the second opening. In some embodiments, the second bonding layer has a first projection projected onto the second bonding surface, the second interconnect layer has a second projection projected onto the second bonding surface, and the first projection is disposed centrally symmetric based on the second projection. In some embodiments, the first bonding layer has a third projection projected onto the second bonding surface, and when the second semiconductor structure and the first semiconductor structure are in the standard bonding position, the first projection and the thir