CN-122028702-A - Electronic chip comprising crack detection device

Abstract

Embodiments of the present disclosure relate to an electronic chip including a crack detection device. An electronic chip includes a crack detection device formed inside and on top of a substrate or on top of a substrate. The device includes conductive paths alternately formed by lower conductive strips and upper conductive strips, wherein each lower strip includes first and second conductive vias in contact with the lower conductive strip, third and fourth conductive vias in contact with the upper strip and another upper strip, respectively, and first and second conductive traces connecting the first and third vias and the second and fourth vias, respectively. The first and second through holes are positioned in vertical alignment with the first and second ends of the lower strap, respectively, and the third and fourth through holes are positioned in vertical alignment with one end of the upper strap and one end of the other upper strap, respectively.

Inventors

• G. Zhu An

Assignees

• 意法半导体国际公司

Dates

Publication Date

20260512

Application Date

20251106

Priority Date

20241106

Claims (20)

1. 1. A crack detection device, comprising: Lower and upper conductive strips alternately connected in series, Wherein the mutually connected surfaces of the conductive strips are positioned entirely within 25% of the length of the conductive strips closest to the ends of the conductive strips.
2. 2. A crack detection device, comprising: Lower and upper conductive strips alternately connected in series, Wherein the mutually connected surfaces of the conductive strips are positioned entirely within 20% of the length of the conductive strips closest to the ends of the conductive strips.
3. 3. The device of claim 1 or 2, wherein at least 80% of the length of the device is occupied by the upper conductive strip when viewed from above and at least 80% of the length of the device is occupied by the lower conductive strip when viewed from below.
4. 4. The device of claim 1 or 2, wherein the lower conductive strip is made of a doped semiconductor material and the upper conductive strip is made of a metal.
5. 5. The device of claim 1 or 2, wherein the lower and upper conductive strips define conductive paths between first and second electrical connection terminals, respectively, of the device.
6. 6. The device of claim 5, wherein for each lower conductive strip, the conductive path comprises: a first conductive via on top of and in contact with the lower conductive strip; a second conductive via on top of and in contact with the lower conductive strip; a third conductive via under and in contact with the overlying upper conductive strip; A fourth conductive via under and in contact with another overlying upper conductive strip; at least one first intermediate conductive trace connecting the first conductive via and the third conductive via, and At least one second intermediate conductive trace connecting the second conductive via and the fourth conductive via; wherein the first conductive via is positioned in vertical alignment with a first end of the lower conductive strip and the second conductive via is positioned in alignment with a second end of the lower conductive strip, and Wherein the third conductive via is positioned in vertical alignment with one end of the overlying conductive strip and the fourth conductive via is positioned in vertical alignment with one end of the other overlying conductive strip.
7. 7. The device of claim 6, wherein: the first conductive via is positioned in vertical alignment with a central portion of the overlying upper conductive strip; the second conductive via is positioned in vertical alignment with a central portion of the other overlying upper conductive strip; The third conductive via being positioned in vertical alignment with a central portion of the lower conductive strip, and The fourth conductive via is positioned in vertical alignment with the central portion of the lower conductive strip.
8. 8. The device of claim 7, wherein for each lower conductive strip, the central portion of the lower conductive strip occupies less than 50% of a length of the lower conductive strip.
9. 9. The device of claim 6, wherein: the fourth conductive via is aligned with the second conductive via; The fourth conductive via being positioned in vertical alignment with the second end of the lower conductive layer, and The second conductive via is positioned in vertical alignment with the end of the other overlying conductive strip.
10. 10. The device of claim 9, wherein the third conductive via is positioned in vertical alignment with a middle portion of the lower conductive strip located near the second end portion of the lower conductive strip, the middle portion being located between a central portion of the lower conductive strip and the second end portion.
11. 11. The device of claim 6, wherein for each lower conductive strip, the first via is positioned entirely in vertical alignment with 25% of a length of the strip furthest from the second end of the lower conductive strip, and the second via is positioned entirely in vertical alignment with 25% of a length of the lower conductive strip furthest from the first end of the lower conductive strip.
12. 12. The device of claim 1 or 2, wherein the lower conductive strip is made of silicon.
13. 13. The device of claim 1 or 2, formed in and on a semiconductor substrate, wherein the semiconductor substrate comprises a doped portion of a first conductivity type, the lower conductive strip being formed entirely in the doped portion of the semiconductor substrate.
14. 14. The device of claim 1 or 2, wherein the lower conductive strips are separated by insulation trenches in pairs.
15. 15. A device according to claim 1 or 2, wherein each lower conductive strip is separated from an adjacent lower conductive strip by a distance in the range 5nm to 10 μm.
16. 16. A device according to claim 1 or 2, wherein each upper conductive strip is spaced apart from an adjacent upper conductive strip by a distance in the range 20nm to 10 μm.
17. 17. An electronic chip comprising the crack detection device of claim 1 or 2, wherein the electronic chip is defined by an edge, and the crack detection device is disposed between the edge of the electronic chip and an electronic circuit area of the electronic chip.
18. 18. An electronic chip, comprising: Semiconductor substrate, and A crack detection device formed inside the semiconductor substrate and on top of the semiconductor substrate, or formed on top of the semiconductor substrate; The crack detection device includes a serpentine conductive path between a first electrical connection terminal and a second electrical connection terminal of the device, the serpentine conductive path including an alternation of lower and upper conductive strips connected in series; Wherein the serpentine conductive path comprises for each lower conductive strip: a first conductive via on top of and in contact with the lower conductive strip; a second conductive via on top of and in contact with the lower conductive strip; a third conductive via under and in contact with the overlying upper conductive strip; A fourth conductive via under and in contact with another overlying upper conductive strip; at least one first intermediate conductive trace connecting the first conductive via and the third conductive via, and At least one second intermediate conductive trace connecting the second conductive via and the fourth conductive via; Wherein the first conductive via is positioned in vertical alignment with a first end of the lower conductive strip and the second conductive via is positioned in alignment with a second end of the lower conductive strip; Wherein the third conductive via is positioned in vertical alignment with one end of the overlying upper conductive strip and the fourth conductive via is positioned in vertical alignment with one end of the other overlying upper conductive strip; Wherein at least 80% of the length of the crack detection device is occupied by the upper conductive strip in a top view and at least 80% of the length of the crack detection device is occupied by the lower conductive strip in a bottom view, and Wherein the lower conductive strip is made of a doped semiconductor material and the upper conductive strip is made of a metal.
19. 19. The electronic chip of claim 18, wherein the conductive vias in contact with the lower conductive strips are positioned entirely opposite 25% of the length of the lower conductive strips nearest each end, and wherein the conductive vias in contact with the upper conductive strips are positioned entirely opposite 25% of the length of the upper conductive strips nearest each end.
20. 20. The electronic chip of claim 18, wherein for each lower conductive strip, the first via is positioned entirely in vertical alignment with 25% of the length of the strip furthest from the second end of the lower conductive strip, and the second via is positioned entirely in vertical alignment with 25% of the length of the lower conductive strip furthest from the first end of the lower conductive strip.

Description

Electronic chip comprising crack detection device Priority claim The present application claims priority from french patent application FR 2412129 filed at month 11 and 6 of 2024, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law. Technical Field The present disclosure relates generally to electronic chips or integrated circuits, and in particular to electronic chips comprising crack detection devices, for example, integrated in a sealing ring. Background In industry, most electronic devices are manufactured in series. Thus, a plurality of electronic chips are typically fabricated inside and on top of the same semiconductor substrate (e.g., the same semiconductor wafer). The electronic chips may then be separated, either singulated (individualize) or singulated (singulate), so as to be able to be used, for example, alone or in electronic devices that include other components. Such singulation is typically performed by cutting, for example by means of a saw. During such singulation, for example during dicing of a semiconductor wafer, cracks may form at one edge of the chip and propagate into the chip. Such cracks may cause malfunction of the electronic circuit of the electronic chip. Furthermore, cracks may form during the lifetime of the chip, in particular at one edge of the chip, for example due to temperature variations of the electronic chip. In order to protect the electronic chip, in particular during manufacture, singulation or during use thereof, the electronic chip may comprise a sealing ring at its periphery. The purpose of the sealing ring is to prevent cracks from propagating from the edge to the electronic circuit area of the chip. The purpose of the sealing ring is also to prevent moisture penetration into the active area of the chip. However, the seal ring does not always prevent the formation and propagation of cracks in the electronic chip. Thus, the chip may comprise crack detection means, for example, incorporated in the sealing ring. The crack detection device may be used to test the integrity of the chip at the time of manufacture (e.g., after a dicing step) or during use of the chip. It is desirable to be able to at least partially improve electronic chips, and in particular to improve crack detection devices incorporated in electronic chips. Disclosure of Invention In an embodiment, an electronic chip includes a semiconductor substrate, and a crack detection device formed on the inside and on top of the semiconductor substrate, the crack detection device including a serpentine conductive path between first and second electrical connection terminals of the device, the serpentine conductive path including, for each lower conductive strip, an alternation of lower and upper conductive strips connected in series, a first conductive via on top of the lower conductive strip and in contact with the lower conductive strip, a second conductive via on top of the lower conductive strip and in contact with the lower conductive strip, a third conductive via under and in contact with the upper conductive strip of the device, a fourth conductive via under and in contact with the upper conductive strip of the other upper conductive strip, at least one first intermediate conductive via connecting the first conductive via and the third conductive via, and a second conductive via on top of the lower conductive strip and in contact with the lower conductive strip, the second conductive via positioned in vertical alignment with the upper conductive strip at least one end of the upper conductive strip of the other upper conductive strip, the second conductive via being aligned with the vertical conductive strip at least one end of the upper conductive strip, the second conductive via being positioned in vertical alignment with the vertical conductive strip at least one end of the upper conductive strip of the other upper conductive strip, the second conductive via being aligned with the vertical conductive via 80, and at least 80% of the length of the crack detection device is occupied by the lower conductive strip in a bottom view, and wherein the lower conductive strip is made of a doped semiconductor material and the upper conductive strip is made of metal. According to an embodiment, in a crack detection device, a first conductive via is positioned in alignment with a central portion of an overlying upper conductive strip, a second conductive via is positioned in vertical alignment with a central portion of another overlying upper conductive strip, a third conductive via is positioned in vertical alignment with a central portion of a lower conductive strip, and a fourth conductive via is positioned in vertical alignment with the central portion of the lower conductive strip. According to an embodiment, in the crack detection device, the fourth conductive via is aligned with the second conductive via, the fourth conductive via is positioned