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CN-122028704-A - Test pad structure for semiconductor device test and semiconductor device

CN122028704ACN 122028704 ACN122028704 ACN 122028704ACN-122028704-A

Abstract

The application provides a test pad structure for testing a semiconductor device and the semiconductor device, wherein the semiconductor device comprises a wafer, a plurality of chips are arranged on the wafer, a scribing area is arranged at the periphery of each chip, the test pad structure is arranged in the scribing area and comprises a pad main body, at least one blocking structure extending along the length direction of the scribing area where the pad main body is arranged in the pad main body, each blocking structure is respectively positioned in the edge area of the pad main body, the total length of each blocking structure is smaller than the length of the pad main body in the length direction of the scribing area, each blocking structure comprises a plurality of sub-blocking structures which are sequentially arranged at intervals along the length direction of the scribing area, and each sub-blocking structure penetrates through the pad main body in the thickness direction of the pad main body, wherein the length direction of the scribing area is the scribing direction of the wafer. The application can limit the crack on the test pad structure in the blocking structure, and improve the yield of the device.

Inventors

  • LI ZHONGREN
  • ZHAO XIAOYAN
  • HE QIQING

Assignees

  • 芯联集成电路制造股份有限公司

Dates

Publication Date
20260512
Application Date
20260120

Claims (10)

  1. 1. A test pad structure for testing a semiconductor device, the semiconductor device comprising a wafer on which a plurality of chips are disposed, a scribe area being provided at a periphery of each of the chips, the test pad structure being disposed in the scribe area, the test pad structure comprising: the bonding pad comprises a bonding pad body, wherein at least one blocking structure extending along the length direction of a scribing area where the bonding pad body is arranged in the bonding pad body, each blocking structure is respectively positioned in the edge area of the bonding pad body, and the total length of each blocking structure is smaller than the length of the bonding pad body in the length direction of the scribing area; Each blocking structure comprises a plurality of sub-blocking structures which are sequentially arranged at intervals along the length direction of the scribing area, each sub-blocking structure penetrates through the pad main body along the thickness direction of the pad main body, and the length direction of the scribing area is the scribing direction of the wafer.
  2. 2. The test pad structure of claim 1, wherein the number of the blocking structures is two, the two blocking structures are respectively arranged at two opposite edge regions of the pad body, and the spacing direction of the two blocking structures is perpendicular to the length direction of the dicing area.
  3. 3. The test pad structure of claim 1, wherein a projected shape of each sub-barrier structure on the wafer surface is a polyline, the polyline is formed by a first line segment, a second line segment and a third line segment, the second line segment connects the first line segment and the third line segment, wherein the first line segment and the third line segment extend along a length direction of the scribe area, the second line segment forms a first included angle with the first line segment at a connection point, and the third line segment forms a second included angle with the second line segment at a connection point.
  4. 4. The test pad structure of claim 3, wherein the zigzag shape has a first included angle greater than or equal to 90 degrees and less than 180 degrees and a second included angle greater than or equal to 90 degrees and less than 180 degrees.
  5. 5. The test pad structure of claim 1, Adjacent sub-barrier structures in each of the barrier structures are separated from each other, and/or And/or the sub-barrier structures of different barrier structures are aligned one by one in a direction perpendicular to the length direction of the dicing area.
  6. 6. The test pad structure of claim 1, wherein the pad body remains structurally connected beyond the location of the sub-barrier structure.
  7. 7. The test pad structure of claim 1, wherein the material of the pad body comprises copper, aluminum, or copper-aluminum alloy.
  8. 8. The test pad structure of claim 1, wherein the sub-barrier structure is a trench structure or a dielectric structure, the barrier structure configured to confine a crack within the barrier structure during wafer dicing, preventing crack propagation to the chip.
  9. 9. A semiconductor device, comprising: A wafer; A plurality of chips disposed on the wafer; a dicing area arranged at the periphery of each chip; At least one test pad structure is provided in the scribe area, the test pad structure being as claimed in any one of claims 1-8.
  10. 10. The semiconductor device according to claim 9, further comprising: a seal ring formed on the wafer and located between the die and the scribe area; The passivation layer at least covers the sealing ring and the test pad structure, wherein the sealing ring comprises a plurality of metal layers and a plurality of conductive through holes which are arranged at intervals, adjacent metal layers are separated by a dielectric layer, and any two adjacent metal layers in the metal layers are electrically connected through at least one conductive through hole.

Description

Test pad structure for semiconductor device test and semiconductor device Technical Field The present application relates to the field of semiconductor technology, and in particular, to a test pad structure for testing a semiconductor device and a semiconductor device. Background In the manufacturing process of semiconductor devices, chip packaging is an indispensable key step, and wafer dicing is used as a core step in the packaging process, which has a decisive influence on the quality and reliability of the final chip. With the continued miniaturization of multi-chip functions and advanced packaging, ultra-thin wafer dicing, smaller chip area, and narrower scribe areas have become a mainstream design trend. The wafer needs to undergo thinning and cutting procedures after the front process is finished and before the wafer enters the package, and when the wafer is mechanically cut, various damages are easily generated on the edge of the scribing area due to factors such as stress, and the like, including edge breakage, cracks, scratches and the like, and the cutting damages are particularly serious on the narrower scribing area. In the related art, in order to avoid mechanical damage of a dicing area, especially the position of a test pad (TESTKEY PAD), in the wafer dicing process, a method is generally adopted, namely, firstly, the width of the dicing area is increased so as to increase the safety distance from a dicing edge to a chip area, but the method can lose the effective area of a wafer, reduce the number of available effective chips (die) of a single wafer, secondly, dicing grooves are added at two ends of the dicing area, namely, grooves are formed in a passivation layer, the method can reduce the size of the dicing area, avoid stress diffusion and crack expansion caused by friction between a cutter and the test pad in dicing, but the method can reduce the protection effect of the passivation layer, meanwhile, due to the existence of the dicing grooves, the size of the dicing area can be reduced, thirdly, the size of the test pad on the dicing area is reduced, the smaller the test pad is the smaller the damage suffered when the wafer is diced, but the small test pad can increase the alignment difficulty of a probe in the wafer acceptability test process (WAFER ACCEPTANCE TEST, WAT), and the test yield and the data reliability are affected. There is therefore a need for an improvement to at least partially solve the above-mentioned problems. Disclosure of Invention In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the application is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In order to solve the problems existing at present, the application provides a test pad structure for testing a semiconductor device, the semiconductor device comprises a wafer, a plurality of chips are arranged on the wafer, a scribing area is arranged at the periphery of each chip, the test pad structure is arranged in the scribing area, the test pad structure comprises a pad main body, at least one blocking structure extending along the length direction of the scribing area where the pad main body is arranged in the pad main body, each blocking structure is respectively positioned in the edge area of the pad main body, the total length of each blocking structure is smaller than the length of the pad main body in the length direction of the scribing area, each blocking structure comprises a plurality of sub-blocking structures which are sequentially arranged at intervals along the length direction of the scribing area, and each sub-blocking structure penetrates through the pad main body along the thickness direction of the pad main body, wherein the length direction of the scribing area is the scribing direction of the wafer. The number of the blocking structures is two, the two blocking structures are respectively arranged at two opposite edge areas of the bonding pad main body, and the interval direction of the two blocking structures is perpendicular to the length direction of the scribing area. The projection shape of each sub-blocking structure on the surface of the wafer is a polygonal shape, the polygonal shape is composed of a first line segment, a second line segment and a third line segment, the second line segment is connected with the first line segment and the third line segment, the first line segment and the third line segment extend along the length direction of the scribing area, a first included angle is formed between the second line segment and the first line segment at a connecting position, and a second included angle is formed between the third line segment and the second line segment at a connecting position. Illustratively, the zigzag shape has a f