CN-122028707-A - Method, system, equipment and preparation method of transistor for detecting parasitic capacitance

Abstract

The application provides a method, a system, equipment and a preparation method of a transistor for detecting parasitic capacitance, wherein the method comprises the steps of providing a first transistor, a second transistor and a third transistor; the first transistor comprises front source drain metal, a back source drain contact area of the first transistor is filled with an insulating medium, the second transistor comprises back source drain metal, a front source drain contact area of the second transistor is filled with an insulating medium, the third transistor comprises front source drain metal and back source drain metal, a first grid capacitance of the first transistor, a second grid capacitance of the second transistor and a third grid capacitance of the third transistor are measured respectively, and parasitic capacitance from the front source drain metal to the grid and parasitic capacitance from the back source drain metal to the grid are determined according to the first grid capacitance, the second grid capacitance and the third grid capacitance.

Inventors

• WU HENG
• YAN XIANGYU
• LIN MINGMIN
• HUANG RU

Assignees

• 北京大学

Dates

Publication Date

20260512

Application Date

20260123

Claims (10)

1. 1. A method of detecting parasitic capacitance, comprising: providing a first transistor, a second transistor and a third transistor, wherein the first transistor comprises front-side source-drain metal, a back-side source-drain contact area of the first transistor is filled with an insulating medium, the second transistor comprises back-side source-drain metal, a front-side source-drain contact area of the second transistor is filled with an insulating medium, and the third transistor comprises front-side source-drain metal and back-side source-drain metal; measuring a first gate capacitance of the first transistor, a second gate capacitance of the second transistor, and a third gate capacitance of the third transistor, respectively; and determining the parasitic capacitance from the front source drain metal to the grid and the parasitic capacitance from the back source drain metal to the grid according to the first grid capacitance, the second grid capacitance and the third grid capacitance.
2. 2. The method of claim 1, wherein determining the front-side source-drain metal-to-gate parasitic capacitance and the back-side source-drain metal-to-gate parasitic capacitance from the first gate capacitance, the second gate capacitance, and the third gate capacitance comprises: determining parasitic capacitance from the source and drain metal on the front surface to the grid electrode according to the difference value of the third grid electrode capacitance and the second grid electrode capacitance; And determining parasitic capacitance from the back source drain metal to the grid according to the difference value of the third grid capacitance and the first grid capacitance.
3. 3. The method of claim 1, wherein the first gate capacitance, the second gate capacitance, and the third gate capacitance are measured using the same test connection method.
4. 4. A method according to claim 3, wherein the test connection method comprises: Providing a device to be tested, wherein the device to be tested comprises at least one transistor, and the transistor is any one of the first transistor, the second transistor and the third transistor, and comprises a source-drain interconnection through hole, a back source-drain extraction structure and a grid extraction structure; The back source drain lead-out structures in each transistor are connected in parallel and electrically connected to a first test node; the grid electrode leading-out structures in each transistor are connected in parallel and electrically connected to a second test node, wherein the second test node is used for applying alternating current test signals; and connecting the source-drain interconnection through holes in each transistor in parallel and electrically connecting the source-drain interconnection through holes to a third test node, wherein the third test node is grounded.
5. 5. The method according to claim 4, wherein; in the case that the transistor is the first transistor, one end of the source-drain interconnection through hole is connected with the front source-drain metal, and the other end is connected with an insulating medium filled in the back source-drain contact area; In the case that the transistor is the second transistor, one end of the source-drain interconnection through hole is connected with the back source-drain metal, and the other end is connected with an insulating medium filled in the front source-drain contact area; and in the case that the transistor is the third transistor, one end of the source-drain interconnection through hole is connected with the front source-drain metal, and the other end is connected with the back source-drain metal.
6. 6. A method according to claim 3, wherein the test connection method comprises: Providing a device to be tested, wherein the device to be tested comprises at least one transistor, and the transistor is any one of the first transistor, the second transistor and the third transistor, and comprises a front source drain extraction structure, a back source drain extraction structure and a grid extraction structure; The back source drain lead-out structures in each transistor are connected in parallel and electrically connected to a first test node; the grid electrode leading-out structures in each transistor are connected in parallel and electrically connected to a second test node, wherein the second test node is used for applying alternating current test signals; Connecting the front source drain lead-out structures in each transistor in parallel and electrically connecting the front source drain lead-out structures to a fourth test node; the fourth test node is electrically connected to a third test node through a test node via, the test node via is configured to provide an electrical connection path between the third test node and the fourth test node, and the third test node is grounded.
7. 7. A method for manufacturing a transistor, wherein the transistor is applied to the method for detecting parasitic capacitance according to any one of claims 1 to 6, the method comprising: Forming an active structure on a substrate; forming a source drain epitaxy based on the active structure; etching a groove on the first surface of the source drain epitaxy to form a front source drain contact area; filling the front source-drain contact region: Turning over the wafer; Etching a groove on the second surface of the source drain epitaxy to form a back source drain contact area; And filling the back source drain contact area, wherein the material filling the front source drain contact area is conductive material or insulating medium.
8. 8. The method of claim 7, wherein the step of determining the position of the probe is performed, Filling conductive materials in the front source-drain region, and under the condition that the back source-drain region is filled with an insulating medium, the transistor is a first transistor; The transistor is a second transistor under the condition that the front source-drain region is filled with an insulating medium and the back source-drain region is filled with a conductive material; and the transistor is a third transistor in the case that the front-side source-drain region is filled with a conductive material and the back-side source-drain region is filled with a conductive material.
9. 9. A parasitic capacitance detection system for performing the method of detecting parasitic capacitance of any one of claims 1 to 6, the detection system comprising: The device comprises a measuring module, a first transistor, a second transistor, a third transistor, a first transistor, a second transistor, a back source-drain contact area and a back source-drain contact area, wherein the first gate capacitance of a first device to be measured, the second gate capacitance of a second device to be measured and the third gate capacitance of a third device to be measured are respectively measured; And the calculation module is used for determining the parasitic capacitance from the front source drain metal to the grid and the parasitic capacitance from the back source drain metal to the grid according to the first grid capacitance, the second grid capacitance and the third grid capacitance.
10. 10. A detection apparatus, characterized by comprising: one or more processors; storage means for storing one or more programs which when executed by the one or more processors cause the one or more processors to perform the method of detecting parasitic capacitance of any of claims 1 to 6.

Description

Method, system, equipment and preparation method of transistor for detecting parasitic capacitance Technical Field The present application relates to semiconductor detection technology, and in particular, to a method, a system, a device, and a method for manufacturing a transistor for detecting parasitic capacitance. Background At present, the test of the parasitic capacitance inside the transistor depends on a computer simulation technology, and the total parasitic capacitance obtained by the test of the method inherently contains several capacitances (such as source-drain epitaxial layer to gate capacitance and source-drain metal to gate capacitance), so that the separation and extraction of the parasitic capacitances cannot be realized. Disclosure of Invention The embodiment of the application provides a method, a system and equipment for detecting parasitic capacitance and a preparation method of a transistor, which can solve the problem that the parasitic capacitance from source drain metal to a grid electrode is inherently contained. The technical scheme of the embodiment of the application is realized as follows: The embodiment of the application provides a method for detecting parasitic capacitance, which comprises the steps of providing a first transistor, a second transistor and a third transistor, wherein the first transistor comprises front source drain metal, a back source drain contact area of the first transistor is filled with an insulating medium, the second transistor comprises back source drain metal, a front source drain contact area of the second transistor is filled with an insulating medium, the third transistor comprises front source drain metal and back source drain metal, a first gate capacitance of the first transistor, a second gate capacitance of the second transistor and a third gate capacitance of the third transistor are measured respectively, and the parasitic capacitance from the front source drain metal to the gate and the parasitic capacitance from the back source drain metal to the gate are determined according to the first gate capacitance, the second gate capacitance and the third gate capacitance. In some possible embodiments, determining the parasitic capacitance of the front source drain metal to the gate and the parasitic capacitance of the back source drain metal to the gate according to the first gate capacitance, the second gate capacitance and the third gate capacitance comprises determining the parasitic capacitance of the front source drain metal to the gate according to the difference between the third gate capacitance and the second gate capacitance, and determining the parasitic capacitance of the back source drain metal to the gate according to the difference between the third gate capacitance and the first gate capacitance. In some possible embodiments, the same test connection method is used when measuring the first gate capacitance, the second gate capacitance, and the third gate capacitance. In some possible embodiments, the test connection method comprises the steps of providing a device to be tested, enabling the device to be tested to comprise at least one transistor, enabling the transistor to be any one of a first transistor, a second transistor and a third transistor, enabling the transistor to comprise a source-drain interconnection through hole, a back source-drain extraction structure and a grid extraction structure, enabling the source-drain interconnection through hole to provide an electric connection path between a front source-drain contact area and a back source-drain contact area, enabling the back source-drain extraction structure in each transistor to be connected in parallel and electrically connected to a first test node, enabling the first test node to be grounded, enabling the grid extraction structure in each transistor to be connected in parallel and electrically connected to a second test node, enabling the source-drain interconnection through hole in each transistor to be connected in parallel and electrically connected to a third test node, and enabling the third test node to be grounded. In some possible embodiments, in the case of the transistor being a first transistor, one end of the source-drain interconnection via is connected to the front-side source-drain metal, and the other end is connected to the insulating medium filled in the back-side source-drain contact region, in the case of the transistor being a second transistor, one end of the source-drain interconnection via is connected to the back-side source-drain metal, and the other end is connected to the insulating medium filled in the front-side source-drain contact region, and in the case of the transistor being a third transistor, one end of the source-drain interconnection via is connected to the front-side source-drain metal, and the other end is connected to the back-side source-drain metal. In some possible embodiments, the test connection method comprises