CN-122028708-A - Method, system, equipment and preparation method of transistor for detecting parasitic resistance

CN122028708ACN 122028708 ACN122028708 ACN 122028708ACN-122028708-A

Abstract

The application provides a method, a system and equipment for detecting parasitic resistance and a preparation method of a transistor. The method includes providing a device to be tested, each transistor in the device to be tested comprises a front source drain metal and a back source drain metal which are oppositely arranged, applying an excitation current between two adjacent front source drain metals and measuring a generated bottom channel voltage value, applying an excitation current between two adjacent back source drain metals and measuring a generated top channel voltage value, applying an excitation current between the oppositely arranged front source drain metal and back source drain metal and measuring a generated middle channel voltage value, determining a parasitic resistance value of each transistor based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value of an excitation source and the voltage value, wherein the parasitic resistance value comprises at least one of a front side contact resistance value, a back contact resistance value, a front epitaxial resistance value, a back epitaxial resistance value and a channel resistance value.

Inventors

WU HENG
YAN XIANGYU
LIN MINGMIN
HUANG RU

Assignees

北京大学

Dates

Publication Date: 20260512
Application Date: 20260123

Claims (11)

1. A method of detecting parasitic resistance, comprising: The method comprises the steps of providing a device to be tested, wherein the device to be tested comprises at least three transistors arranged side by side in a first direction, and each transistor comprises a front source drain metal and a back source drain metal which are oppositely arranged; Applying exciting current between two adjacent front source drain metals, and measuring the generated bottom channel voltage value; Applying the excitation current between two adjacent back source drain metals, and measuring the generated top channel voltage value; Applying exciting current between the oppositely arranged front source drain metal and back source drain metal, and measuring the generated middle channel voltage value; And determining a parasitic resistance value of each transistor based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value of the excitation source and the voltage value, wherein the parasitic resistance value comprises at least one of a front side contact resistance value, a back side contact resistance value, a front side epitaxial resistance value, a back side epitaxial resistance value and a channel resistance value.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises, A pair of front source drain metal and back source drain metal are shared between two adjacent transistors; the front-side source-drain metals of the at least three transistors arranged side by side in the first direction comprise a first front-side source-drain metal, a second front-side source-drain metal, a third front-side source-drain metal and a fourth front-side source-drain metal; The back source drain metals of the three transistors arranged side by side in the first direction comprise a first back source drain metal, a second back source drain metal, a third back source drain metal and a fourth back source drain metal; Each transistor further comprises a front source drain extraction structure and a back source drain extraction structure, wherein the front source drain extraction structure is electrically connected with the front source drain metal, and the back source drain extraction structure is electrically connected with the back source drain metal.
3. The method of claim 2, wherein applying an excitation current between two adjacent front-side source-drain metals and measuring the resulting bottom channel voltage value comprises: the excitation current flows in from the third front-face source-drain metal and flows out from the second front-face source-drain metal through a test node electrically connected with the second front-face source-drain metal and the third front-face source-drain metal; And measuring the bottom channel voltage value through a test node electrically connected with the second back source drain metal and the third back source drain metal in a first circuit path generated by the excitation current.
4. The method of claim 2, wherein applying the excitation current between two adjacent back-side source-drain metals and measuring the resulting top channel voltage value comprises: the excitation current flows in from the third back surface source drain metal and flows out from the second back surface source drain metal through a test node electrically connected with the third back surface source drain metal and the second back surface source drain metal; and measuring the top channel voltage value through a test node electrically connected with the second front-side source-drain metal and the third front-side source-drain metal in a second circuit path generated by the excitation current.
5. The method of claim 2, wherein applying an excitation current between the oppositely disposed front-side source-drain metal and back-side source-drain metal and measuring the resulting middle channel voltage value comprises: The excitation current flows in from the second front-side source-drain metal and flows out from the second back-side source-drain metal through a test node electrically connected with the second front-side source-drain metal and the second back-side source-drain metal; And in a third circuit path generated by the excitation current, measuring the middle channel voltage value through a test node electrically connected with the first back source drain metal.
6. The method of claim 2, wherein a first source-drain interconnect via is disposed between the second front-side source-drain metal and the second back-side source-drain metal, and a second source-drain interconnect via is disposed between the third front-side source-drain metal and the third back-side source-drain metal; the method further comprises the steps of: electrically connecting a first test node to the second front side source drain metal through the first source drain interconnect via; Electrically connecting a sixth test node to the third front side source drain metal through the second source drain interconnect via; And through the back source drain lead-out structure, electrically connecting a second test node to the second back source drain metal, electrically connecting a third test node to the first back source drain metal, electrically connecting a fourth test node to the fourth back source drain metal, and electrically connecting a fifth test node to the third back source drain metal.
7. The method according to claim 2, wherein the method further comprises: the first through hole is used for providing a conduction path between the first test node and the eighth test node, and the eighth test node is electrically connected with the second front source drain metal; The second through hole is used for providing a conduction path between the sixth test node and the ninth test node, and the ninth test node is electrically connected with the third front source drain metal; And through the back source drain lead-out structure, electrically connecting a second test node to the second back source drain metal, electrically connecting a third test node to the first back source drain metal, electrically connecting a fourth test node to the fourth back source drain metal, and electrically connecting a fifth test node to the third back source drain metal.
8. The method of claim 1, wherein the determining the parasitic resistance value of each transistor based on the bottom channel potential value, the middle channel potential value, the top channel potential value, the current value of the stimulus, and the voltage value comprises at least one of: Calculating to obtain the channel resistance value based on the current value, the bottom channel potential value, the middle channel potential value and the top channel potential value of the excitation source; Calculating to obtain the front epitaxial resistance value and the back epitaxial resistance value based on the current value and the voltage value of the excitation source and the potential value of the middle channel; Calculating to obtain the front contact resistance value based on the front epitaxial resistance value, the current value and the voltage value of the excitation source and the middle channel potential value; and calculating the back contact resistance value based on the back epitaxial resistance value, the middle channel resistance value and the current value of the excitation source.
9. A method for manufacturing a transistor, wherein the transistor is applied to the method for detecting parasitic resistance according to any one of claims 1 to 8, the method comprising: Forming an active structure on a substrate; forming a source drain epitaxy based on the active structure; Forming front source drain metal on the first surface of the source drain epitaxy, and forming a front source drain lead-out structure on the front source drain metal; Turning over the wafer; And forming back source-drain metal on the second surface of the source-drain epitaxy, and forming a back source-drain lead-out structure on the back source-drain metal.
10. A parasitic resistance detection system for performing the method of detecting parasitic resistance of any one of claims 1 to 8, the detection system comprising: The first measuring module is used for acquiring a bottom channel voltage value of the device to be measured; the device to be tested comprises at least three transistors arranged side by side in a first direction, wherein each transistor comprises a front source drain metal and a back source drain metal which are oppositely arranged, and the bottom channel voltage value is generated by applying exciting current between two adjacent front source drain metals; the second measuring module is used for obtaining a top channel voltage value of the device to be measured, wherein the top channel voltage value is generated by applying the excitation current between two adjacent back source drain metals; the device comprises a first measuring module, a second measuring module and a third measuring module, wherein the first measuring module is used for obtaining a front-side source-drain metal and a back-side source-drain metal of a device to be measured; And the calculating module is used for determining a parasitic resistance value of the device to be tested based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value, the current value and the voltage value of the excitation source, wherein the parasitic resistance value comprises at least one of a front side contact resistance value, a back side contact resistance value, a front side epitaxial resistance value, a back side epitaxial resistance value and a channel resistance value.
11. A test apparatus, comprising: one or more processors; Storage means for storing one or more programs which when executed by the one or more processors cause the one or more processors to perform the method of detecting parasitic resistance of any of claims 1 to 8.

Description

Method, system, equipment and preparation method of transistor for detecting parasitic resistance Technical Field The present application relates to semiconductor detection technology, and in particular, to a method, a system, a device, and a method for manufacturing a transistor for detecting parasitic resistance. Background Under the trend of advanced semiconductor devices towards three-dimensional stacked and double-sided interconnection architecture, accurate measurement of various parasitic resistances inside the devices has become a key challenge for performance characterization and process optimization. The conventional resistance testing method is generally based on the assumption of single-side contact and planar current paths, and is difficult to be applied to a novel device structure with a vertical stacked channel, double-sided electrodes and complex current paths, so that resistance contributions of different physical areas cannot be independently analyzed, and further optimization of the device structure is limited. Disclosure of Invention The embodiment of the application provides a method, a system and equipment for detecting parasitic resistance and a preparation method of a transistor, which can realize independent extraction and separation of parasitic resistance of different physical areas in the transistor. The technical scheme of the embodiment of the application is realized as follows: The embodiment of the application provides a method for detecting parasitic resistance, which comprises the steps of providing a device to be detected, wherein the device to be detected comprises at least three transistors which are arranged side by side in a first direction, each transistor comprises a front source drain metal and a back source drain metal which are arranged oppositely, exciting current is applied between two adjacent front source drain metals and a generated bottom channel voltage value is measured, exciting current is applied between two adjacent back source drain metals and a generated top channel voltage value is measured, exciting current is applied between the front source drain metal and the back source drain metal which are arranged oppositely and a generated middle channel voltage value is measured, and the parasitic resistance value of each transistor is determined based on the bottom channel voltage value, the middle channel voltage value, the top channel voltage value and the current value and the voltage value of an exciting source. In some possible embodiments, a pair of front source drain metal and back source drain metal are shared between two adjacent transistors, the front source drain metal of at least three transistors arranged side by side in the first direction comprises a first front source drain metal, a second front source drain metal, a third front source drain metal and a fourth front source drain metal, the back source drain metal of the three transistors arranged side by side in the first direction comprises a first back source drain metal, a second back source drain metal, a third back source drain metal and a fourth back source drain metal, each transistor further comprises a front source drain lead-out structure and a back source drain lead-out structure, the front source drain lead-out structure is electrically connected with the front source drain metal, and the back source drain lead-out structure is electrically connected with the back source drain metal. In some possible embodiments, applying an excitation current between two adjacent front-side source-drain metals and measuring the resulting bottom channel voltage value includes measuring the bottom channel voltage value through a test node electrically connected to the second front-side source-drain metal and the third front-side source-drain metal such that the excitation current flows in from the third front-side source-drain metal and out from the second front-side source-drain metal, and measuring the bottom channel voltage value through a test node electrically connected to the second back-side source-drain metal and the third back-side source-drain metal in a first circuit path generated by the excitation current. In some possible embodiments, applying an excitation current between two adjacent back-side source-drain metals and measuring the resulting top channel voltage value includes measuring the top channel voltage value through a test node electrically connected to the third back-side source-drain metal and the second back-side source-drain metal such that the excitation current flows in from the third back-side source-drain metal and out from the second back-side source-drain metal, and measuring the top channel voltage value through a test node electrically connected to the second front-side source-drain metal and the third front-side source-drain metal in a second circuit path resulting from the excitation current. In some possible embodiments, applying an excitation current between