CN-122028711-A - Method and system for reducing preparation fragmentation rate of ultrathin semiconductor test sample

CN122028711ACN 122028711 ACN122028711 ACN 122028711ACN-122028711-A

Abstract

The application relates to the technical field of semiconductors, in particular to a method and a system for reducing the preparation fragment rate of an ultrathin semiconductor test sample. The method comprises the steps of S1, preparing a sample and a support, namely obtaining an ultrathin semiconductor chip to be tested, processing the ultrathin semiconductor chip to form a sample A to be tested, preparing a support B with the thickness larger than that of the sample A, preparing a layered composite sample preparation body by means of layered bonding, namely preparing an angle matrix, a first bonding layer, a support B, a second bonding layer and the sample A, S3, solidifying and clamping the layered composite sample preparation body, namely cooling and solidifying the layered composite sample preparation body, mounting the solidified layered composite sample preparation body to a sample preparation fixing device, and S4, grinding the sample A in a target grinding posture by means of a controlled grinding medium and an inclined plane so that the sample A forms an inclined plane test area for an extended resistance test. According to the application, the composite sample preparation body is constructed through layered bonding, so that the fragment rate in the sample is reduced, and the success rate of preparing the ultrathin semiconductor chip sample is improved.

Inventors

LIU CONGJI
BU HUI
JIAN MAOYU
GU JIALIN
GONG HONGJIE
CAO LICHUN

Assignees

重庆鹰谷光电股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260327

Claims (10)

1. A method of reducing the rate of fragmentation of an ultrathin semiconductor test sample preparation comprising: S1, preparing a sample and a support, namely acquiring an ultrathin semiconductor chip to be tested, processing the ultrathin semiconductor chip to form a sample A to be tested, and preparing a support B with the thickness larger than that of the sample A, wherein the sample A is a working sample for forming a test inclined plane, and the support B is used for providing rigid support and stress buffering for the sample A in the grinding process; S2, heating the angle matrix to a temperature range for melting the hot-melt adhesive material, coating the hot-melt adhesive material on a preset inclined plane of the angle matrix and attaching the support body B, forming a first adhesive layer between the support body B and the angle matrix, coating the hot-melt adhesive material again on the exposed surface of the support body B and attaching the sample A, and forming a second adhesive layer between the sample A and the support body B to obtain the layered composite sample body of the angle matrix-the first adhesive layer-the support body B-the second adhesive layer-the sample A; s3, solidifying and clamping, namely cooling and solidifying the layered composite sample preparation body, and mounting the solidified layered composite sample preparation body to a sample preparation fixing device so as to enable the surface to be ground of the sample A to maintain a target grinding posture consistent with the inclined surface of the angle matrix on a grinding platform; And S4, grinding the sample A in the target grinding posture by configuring a grinding medium containing a diamond abrasive on a grinding platform and adding a diluent into the grinding medium to regulate and control the viscosity and the lubrication/bearing characteristics of the grinding medium, so that the sample A forms a bevel test area for an extended resistance test.
2. The method according to claim 1, wherein the sample a to be tested is formed by dicing an ultrathin semiconductor chip to be tested, the sample a is a cuboid with a size of x 2x (unit mm), and the test surface of the sample a has a width of x and a length of 2x, wherein x is greater than or equal to 1mm and less than or equal to 3mm.
3. The method of claim 1, wherein the ultra-thin semiconductor chip is an avalanche diode chip or an IGBT chip, and the chip thickness is 100 μm to 200 μm; the support body B is made of a silicon wafer material, and the thickness of the support body B is 500-675 microns; the support B was processed into a rectangular parallelepiped having a size of 1.5x×3x (unit mm).
4. The method according to claim 1, wherein the angle matrix is a cylindrical angle gauge, and the upper surface of the angle matrix is composed of two semicircular inclined planes with a fixed angle alpha with the horizontal plane, and the target grinding posture is used for forming a bevel test area with the same angle as the semicircular inclined planes after grinding the sample A.
5. The method according to claim 1, wherein in step S2, the angular substrate is placed on an electric furnace heating platform for heating; the temperature control range of the heating platform is 100 ℃ so that the hot melt adhesive material is in a molten state, and the hot melt adhesive material is paraffin.
6. The method according to claim 1, wherein in step S2, the short sides of the support B are placed flush along the center line of the angle base when the support B is attached to the predetermined slope of the angle base; and after the support body B is attached to the angle matrix, coating a layer of the hot melt adhesive material on the exposed surface of the support body B, and attaching the sample A.
7. The method according to claim 1, wherein in step S2, the short side of the sample a is placed flush along the short side of the support B and the midpoint of the short side of the sample a coincides with the midpoint of the short side of the support B when the sample a is attached.
8. The method according to claim 1, wherein in step S4, the grinding medium is diamond paste, the diluent is pure water, and the bevel grinding is performed after adding pure water in a ratio of paste to pure water=1:3 and stirring uniformly.
9. The method of claim 1, wherein the thickness of the beveled test region for the extended resistance test is 100 μm to 200 μm.
10. A system for reducing the rate of fragmentation of ultra-thin semiconductor test sample preparations, applied to the method of any one of claims 1 to 9, comprising: The sample preparation module is used for obtaining an ultrathin semiconductor chip to be tested and processing the ultrathin semiconductor chip to form a sample A to be tested, and simultaneously preparing a support body B with the thickness larger than that of the sample A, wherein the sample A is a working sample for forming a test inclined plane, and the support body B is used for providing rigid support and stress buffering for the sample A in the grinding process; The bonding module is used for heating the angle matrix to a temperature range for melting the hot-melt bonding material, coating the hot-melt bonding material on a preset inclined plane of the angle matrix and bonding the support body B, forming a first bonding layer between the support body B and the angle matrix, coating the hot-melt bonding material on the exposed surface of the support body B again and bonding the sample A, forming a second bonding layer between the sample A and the support body B, and obtaining a layered composite sample preparation body of 'the angle matrix-the first bonding layer-the support body B-the second bonding layer-the sample A'; The solidification clamping module is used for cooling and solidifying the layered composite sample preparation body, and mounting the solidified layered composite sample preparation body to a sample preparation fixing device so as to enable the surface to be grinded of the sample A to maintain a target grinding posture consistent with the inclined surface of the angle matrix on the grinding platform; and the grinding module is used for configuring a grinding medium containing diamond abrasive on the grinding platform, regulating and controlling the viscosity and the lubrication/bearing characteristics of the grinding medium by adding diluent into the grinding medium, and grinding the sample A in the target grinding posture to form an inclined plane test area for the extension resistance test.

Description

Method and system for reducing preparation fragmentation rate of ultrathin semiconductor test sample Technical Field The application relates to the technical field of semiconductors, in particular to a method and a system for reducing the preparation fragment rate of an ultrathin semiconductor test sample. Background Extended resistance testing (SPREADING RESISTANCE Profiling, SRP) is a high-precision technique for measuring the longitudinal carrier concentration profile of semiconductor materials. The technology measures the expansion resistance value of each point along the surface of a sample or the ground inclined plane by a micro-stepping point contact probe, and further calculates the depth distribution of the resistivity and the carrier concentration. It is critical in semiconductor process monitoring and device failure analysis. The expanding resistance probe has higher requirements on sample preparation, a cylindrical angle gauge is adopted during sample preparation, and the upper surface of the angle gauge consists of two semicircular inclined planes with a fixed angle alpha with a horizontal plane. After the sample is stuck to the inclined plane, grinding the sample, wherein the back surface of the bearing device is parallel to the horizontal plane during grinding, an inclined plane with the same angle as the semicircular inclined plane is formed on the sample after grinding, and then the sample is fixed on a horizontal floating platform of the extended resistance tester, and analysis and test are performed on the inclined plane through a point selection of an amplified imaging system. Because of the characteristic of the preparation of the extended resistance test sample, the sample preparation fragmentation rate of ultrathin chips (thickness 100-200 μm) such as avalanche diodes, IGBTs and the like is particularly high, and the subsequent test analysis is difficult in most cases, so a new method is needed to solve the technical problems. Disclosure of Invention The present application provides a method for reducing the preparation fragmentation rate of an ultrathin semiconductor test sample to solve the above problems. In a first aspect, the present application provides a method of reducing the rate of fragmentation of an ultrathin semiconductor test sample preparation, the method comprising: S1, preparing a sample and a support, namely acquiring an ultrathin semiconductor chip to be tested, processing the ultrathin semiconductor chip to form a sample A to be tested, and preparing a support B with the thickness larger than that of the sample A, wherein the sample A is a working sample for forming a test inclined plane, and the support B is used for providing rigid support and stress buffering for the sample A in the grinding process; S2, heating the angle matrix to a temperature range for melting the hot-melt adhesive material, coating the hot-melt adhesive material on a preset inclined plane of the angle matrix and attaching the support body B, forming a first adhesive layer between the support body B and the angle matrix, coating the hot-melt adhesive material again on the exposed surface of the support body B and attaching the sample A, and forming a second adhesive layer between the sample A and the support body B to obtain the layered composite sample body of the angle matrix-the first adhesive layer-the support body B-the second adhesive layer-the sample A; s3, solidifying and clamping, namely cooling and solidifying the layered composite sample preparation body, and mounting the solidified layered composite sample preparation body to a sample preparation fixing device so as to enable the surface to be ground of the sample A to maintain a target grinding posture consistent with the inclined surface of the angle matrix on a grinding platform; And S4, grinding the sample A in the target grinding posture by configuring a grinding medium containing a diamond abrasive on a grinding platform and adding a diluent into the grinding medium to regulate and control the viscosity and the lubrication/bearing characteristics of the grinding medium, so that the sample A forms a bevel test area for an extended resistance test. Through the technical scheme, the composite sample preparation body is constructed through layered bonding, so that the success rate of sample preparation of the ultrathin semiconductor chip is remarkably improved. Firstly, the support body B is introduced as a rigid substrate, so that mechanical stress generated in the grinding process is greatly absorbed, and the stress is prevented from directly acting on the ultrathin sample A, thereby reducing the chip rate of the ultrathin chip in the initial grinding stage. Second, the first and second adhesive layers formed of the hot melt adhesive material (e.g., paraffin wax) provide a cushioning effect, further relieving stress concentrations. In addition, the viscosity of the grinding medium is regulated by adding the diluent, so that th