CN-122028713-A - Electrical test structure and test method thereof

CN122028713ACN 122028713 ACN122028713 ACN 122028713ACN-122028713-A

Abstract

The application relates to an electrical test structure and a test method thereof, and relates to the technical field of integrated circuits, wherein the structure comprises a test array, a test circuit and a test circuit, wherein the test array comprises a target transistor and a plurality of peripheral areas which surround the target transistor and are distributed along the radial direction of the test array, and the test circuit is configured to output current to be tested generated by the target transistor and/or the plurality of peripheral areas according to received test voltage; and a gate connected to the target transistor, the plurality of peripheral regions and configured to connect at least one peripheral region to the target transistor in response to the received gate signal, and/or to connect the plurality of peripheral regions to adjust a current to be measured generated by the test array, wherein the test array includes a current to be measured of the peripheral region in a proportional relationship with a current to be measured including only the target transistor. The structure and the method are completely compatible with the existing process technology and are applicable to platforms of different technology nodes. The new structure designed by the method can eliminate the influence of test noise and obtain more accurate MOS leakage.

Inventors

LIU ZHANFENG
WANG XIAOXIAO
MA TING
CHEN XINQUAN
ZHANG MAN

Assignees

合肥晶合集成电路股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260413

Claims (10)

1. An electrical testing structure, comprising: A test array including a target transistor and a plurality of peripheral regions surrounding the target transistor and distributed radially along the test array, configured to output a current to be measured generated by the target transistor and/or the plurality of peripheral regions according to a received test voltage; A gate connected to the target transistor and the plurality of peripheral regions and configured to connect at least one of the peripheral regions to the target transistor in response to a received gate signal and/or to connect the plurality of peripheral regions to adjust a current to be measured generated by the test array; The current to be measured under the condition of no strobe signal is in proportional relation with the current to be measured under the condition of receiving the strobe signal.
2. The electrical test structure of claim 1, wherein the target transistor is configured such that a drain terminal is configured to be connected to the test voltage and a source terminal is configured to output a current to be tested generated by the target transistor; the plurality of peripheral areas comprise N peripheral areas which are sequentially increased in number along the direction deviating from the target transistor, wherein N is more than or equal to 2, and N is an integer; the N peripheral area is configured to have a control end connected with the gate control end of the target transistor, an input end connected with the test voltage, and an output end connected with the source end of the target transistor and used for outputting the current to be tested generated in the N peripheral area.
3. The electrical test structure of claim 2, wherein the N-th peripheral region includes a plurality of auxiliary transistors arranged in a plurality of rows and columns; The auxiliary transistor is configured to have a gate control terminal for forming a control terminal of the Nth peripheral region and connected to a gate control terminal of the target transistor, a drain terminal connected to a drain terminal of another auxiliary transistor, a source terminal for forming an output terminal of the Nth peripheral region and connected to a source terminal of another auxiliary transistor, and a source terminal of the target transistor; the drain terminal of any auxiliary transistor is used for forming the input terminal of the Nth peripheral area.
4. The electrical test structure of claim 3, wherein the gate comprises M gate transistors, M being greater than or equal to 2, M being an integer, the gate ends of the gate transistors being configured to form the input end of the gate; The input end of the first peripheral area is connected with the drain end of the target transistor through a first gating transistor, and the input end of the N-th peripheral area is connected with the input end of the N-1-th peripheral area through an M gating transistor.
5. The electrical test structure of claim 4, wherein the number of strobe signals is equal to the number of strobe transistors; The gate control end is used for independently receiving the Mth gate signal, the drain end is connected with the drain end of any auxiliary transistor in the N peripheral area, and the source end is connected with the drain end of any auxiliary transistor in the N-1 peripheral area or the drain end of the target transistor.
6. The electrical test structure of claim 4, wherein the peripheral region comprises an auxiliary transistor fabricated contemporaneously with the target transistor in the same process step; The conductivity types of the auxiliary transistor and the target transistor are the same; The conductivity types of the different gate transistors are the same or different.
7. The electrical test structure of any one of claims 3-6, wherein the drain terminal of the auxiliary transistor in the same column is adjacent to the source terminal of another auxiliary transistor or the source terminal of the target transistor, or The drain terminal of the auxiliary transistor located in the same column is adjacent to the drain terminal of another of the auxiliary transistors or the drain terminal of the target transistor.
8. The electrical testing structure of any one of claims 3-6, wherein the peripheral region at the outermost periphery comprises at least 6 auxiliary transistors arranged in two rows and two columns.
9. A test method is characterized by comprising an electrical test structure, a gate, a test array and a test module, wherein the test array comprises a target transistor and a plurality of peripheral areas which surround the target transistor and are distributed along the radial direction of the test array, the gate is connected with the target transistor and the plurality of peripheral areas, The method comprises the following steps: Connecting at least one of the peripheral regions to the target transistor in response to the received strobe signal and/or connecting the plurality of peripheral regions to adjust the current to be measured generated by the test array; Outputting a current to be tested generated by the target transistor and/or the plurality of peripheral areas according to the received test voltage based on the test array; and acquiring the leakage current of the target transistor or the leakage current of any peripheral area according to the current to be detected.
10. The method of testing of claim 9, wherein the peripheral region includes an auxiliary transistor fabricated contemporaneously with the target transistor in the same process step; The conductivity types of the auxiliary transistor and the target transistor are the same.

Description

Electrical test structure and test method thereof Technical Field The application relates to the technical field of semiconductor device manufacturing, in particular to an electrical test structure and a test method thereof. Background The wafer acceptance test WAT (Wafer Acceptance Test) is a process evaluation method for measuring electrical parameters of a test device on a wafer dicing channel by a special test device after the wafer preparation is completed and before packaging in a manufacturing factory, and judges whether the wafer meets the electrical specification requirement of a process technology platform according to the test result, and evaluates the process stability and quality stability in the manufacturing process. WAT is generally connected with a test device through a probe card, and after connecting the probe of the probe card with the test device, voltage is applied to the test device to measure corresponding electrical parameters such as leakage current. However, in the related art, the WAT has a technical problem of low measurement accuracy of leakage current due to the influence of the machine environment (such as temperature, humidity, noise) or process variation. Disclosure of Invention Accordingly, it is necessary to provide an electrical testing structure and a testing method thereof, which can at least improve the measurement accuracy of the leakage current in the electrical test. In a first aspect, the present application provides an electrical test structure, comprising: a test array including a target transistor and a plurality of peripheral regions surrounding the target transistor and distributed radially along the test array, configured to output a current to be measured generated by the target transistor and/or the plurality of peripheral regions according to a received test voltage; a gate connected to the target transistor, the plurality of peripheral regions, configured to connect at least one peripheral region to the target transistor in response to the received gate signal, and/or to connect the plurality of peripheral regions to adjust a current to be measured generated by the test array; Wherein the current to be measured in the absence of the strobe signal is proportional to the current to be measured in the presence of the strobe signal. In the electrical test structure provided in the above embodiment, after the test voltage is applied in the leakage test stage, the leakage current of the target transistor and each peripheral area can be obtained independently to detect the local change caused by the process fluctuation, or the peripheral area and the target transistor can be connected through the gate aiming at the problem that the leakage current magnitude of the target transistor is too small, in the test stage, the total current to be tested finally output by the test array is adjusted by controlling the gate to increase the number of times, and finally, the leakage of the target transistor can be obtained by measuring the amplified current and reversely pushing the amplified current by using the known proportion, so that the WAT test precision can be effectively improved. In some embodiments, the target transistor is configured such that the drain terminal is used for connecting a test voltage, and the source terminal is used for outputting a current to be measured generated by the target transistor; The plurality of peripheral areas comprise N peripheral areas which are sequentially increased in number along the direction deviating from the target transistor, wherein N is more than or equal to 2, and N is an integer; The N peripheral area is configured to have a control end connected to the gate control end of the target transistor, an input end for connecting a test voltage, and an output end connected to the source end of the target transistor and for outputting a current to be tested generated in the N peripheral area. In some embodiments, the N-th peripheral region includes a plurality of auxiliary transistors arranged in a plurality of rows and columns; An auxiliary transistor configured such that a gate terminal is used to constitute a control terminal of the nth peripheral region and is connected to a gate terminal of the target transistor, a drain terminal is connected to a drain terminal of another auxiliary transistor, a source terminal is used to constitute an output terminal of the nth peripheral region and is connected to a source terminal of another auxiliary transistor, and a source terminal of the target transistor; The drain terminal of any auxiliary transistor is used for forming the input terminal of the N peripheral region. In some embodiments, the gate comprises M gate transistors, wherein M is more than or equal to 2, and M is an integer; the input end of the first peripheral area is connected with the drain end of the target transistor through the first gating transistor, and the input end of the N-th peripheral area is connected wit