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CN-122028715-A - Semiconductor manufacturing method and semiconductor device

CN122028715ACN 122028715 ACN122028715 ACN 122028715ACN-122028715-A

Abstract

The application provides a semiconductor manufacturing method and a semiconductor device, wherein the manufacturing method comprises the steps of providing a substrate, and sequentially forming a stop layer and a core material layer on the surface of the substrate; the method comprises the steps of patterning a core material layer to form a core layer, forming a side wall material layer covering the top and the side wall of the core layer and the stop layer, forming a filling layer covering the side wall material layer, flattening the filling layer and the side wall material layer to expose the top of the core layer, and removing the rest of the filling layer and the core layer to form a side wall. The semiconductor manufacturing method and the semiconductor device can avoid etching load effect, eliminate defect phenomenon at the top of the side wall, increase process window and improve performance and yield of the semiconductor device.

Inventors

  • WANG LEI

Assignees

  • 深圳市鹏芯微集成电路制造有限公司

Dates

Publication Date
20260512
Application Date
20241105

Claims (10)

  1. 1. A method of manufacturing a semiconductor, the method comprising: providing a substrate, and sequentially forming a stop layer and a core material layer on the surface of the substrate; Patterning the core material layer to form a core layer; forming a side wall material layer covering the top and the side wall of the core layer and the stop layer; Forming a filling layer covering the side wall material layer; flattening the filling layer and the side wall material layer to expose the top of the core layer; And removing the residual filling layer and the core layer to form a side wall.
  2. 2. The method of manufacturing of claim 1, wherein a first hard mask material layer is formed between the stop layer and the core material layer, the core material layer being patterned to form a core layer while the first hard mask material layer is patterned to form a first hard mask layer between the stop layer and the core layer.
  3. 3. The method of manufacturing of claim 1, wherein the sidewall material layer remaining on the stop layer forms a second hard mask layer.
  4. 4. The method of manufacturing of claim 2, wherein a first hard mask material layer is the same material as the sidewall material layer, the first hard mask material layer and the sidewall material layer comprising silicon nitride.
  5. 5. The method of manufacturing of claim 1, wherein the filler layer comprises an oxide formed by flow chemical vapor deposition and the core material layer comprises amorphous silicon.
  6. 6. The method of manufacturing as claimed in claim 1, wherein removing the remaining filler layer and the core layer using a wet etching process includes removing the remaining filler layer using a first etching solution and removing the remaining core layer using a second etching solution.
  7. 7. The method of manufacturing of claim 6, wherein the first etching solution comprises tetramethylammonium hydroxide and the second etching solution comprises dilute hydrofluoric acid.
  8. 8. The method of manufacturing of claim 1, wherein the stop layer comprises an oxide formed by a plasma enhanced process.
  9. 9. The method of manufacturing of claim 1, wherein after the step of removing the remaining filler layer and core layer, further comprising: and etching the substrate by taking the side wall as a mask so as to form a target pattern in the substrate.
  10. 10. A semiconductor device, characterized in that the semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 9.

Description

Semiconductor manufacturing method and semiconductor device Technical Field The present application relates to the field of semiconductor technology, and in particular, to a semiconductor manufacturing method and a semiconductor device. Background With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. Photolithography (photolithography) is a common patterning method and is one of the most critical techniques in semiconductor manufacturing processes. As the critical dimensions of semiconductor devices have been reduced, the conventional photolithography technique for light source has failed to meet the requirements of semiconductor fabrication, and thus, self-aligned double patterning (Self-aligned DoublePatterning, SADP) methods have been developed. The SADP method can obtain a minimum pitch of 1/2 (1/2 pitch) at twice the density of the pattern formed on the substrate by the photolithography process. Therefore, the SADP method is a key technology that can realize smaller-sized patterns. The SADP method is widely used in the manufacture of semiconductor devices because it can achieve excellent line width and pitch control effects, and is advantageous for improving the performance of semiconductor devices. In the related art, a semiconductor device is prepared by adopting a traditional self-aligned double patterning method, and in the side wall (spacer) etching process, because the side wall is influenced by etching load effect, serious defects appear at the top of the etched side wall, and finally the critical dimension etching process of the subsequent device is influenced. Therefore, a new semiconductor manufacturing method is needed to solve the above-mentioned technical problems. Disclosure of Invention In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the application is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In order to solve the problems existing at present, an embodiment of the application provides a semiconductor manufacturing method, which comprises the steps of providing a substrate, sequentially forming a stop layer and a core material layer on the surface of the substrate, patterning the core material layer to form a core layer, forming a side wall material layer covering the top and the side wall of the core layer and the stop layer, forming a filling layer covering the side wall material layer, flattening the filling layer and the side wall material layer to expose the top of the core layer, and removing the rest of the filling layer and the core layer to form a side wall. Illustratively, a first hard mask material layer is formed between the stop layer and the core material layer, the core material layer being patterned to form a core layer while the first hard mask material layer is patterned to form a first hard mask layer between the stop layer and the core layer. Illustratively, the sidewall material layer remaining on the stop layer forms a second hard mask layer. Illustratively, the first hard mask material layer is the same as the sidewall material layer, and the first hard mask material layer and the sidewall material layer comprise silicon nitride. Illustratively, the filler layer comprises an oxide formed by flow chemical vapor deposition and the core material layer comprises amorphous silicon. The method for removing the residual filling layer and the core layer by adopting a wet etching process comprises the steps of removing the residual filling layer by adopting a first etching liquid and removing the residual core layer by adopting a second etching liquid. Illustratively, the first etching solution comprises tetramethylammonium hydroxide and the second etching solution comprises dilute hydrofluoric acid. Illustratively, the stop layer comprises an oxide formed by a plasma enhanced process. The step of removing the remaining filling layer and the core layer further comprises etching the substrate by taking the side wall as a mask to form a target pattern in the substrate. Another aspect of the present application provides a semiconductor device manufactured by the manufacturing method described above. According to the semiconductor manufacturing method and the semiconductor device, the side wall material layer is formed on the top and the side wall of the core layer and the stop layer, and the filling layer covering the side wall material layer is formed, so that the etching load effect is avoided, the defect phenomenon of the top of the side wall is eliminated, the process window is increased, and the performance and the yield of the semiconductor device are improved. Drawings The above and other objects, featur