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CN-122028720-A - Semiconductor memory structure and preparation method thereof

CN122028720ACN 122028720 ACN122028720 ACN 122028720ACN-122028720-A

Abstract

The application discloses a semiconductor memory structure and a preparation method thereof, which can eliminate grooves in the process of filling a plurality of material layers in a groove and improve the yield of the semiconductor memory. The semiconductor memory structure comprises a substrate, at least one first groove positioned on the upper surface of the substrate, a first dielectric layer distributed along the inner wall of the first groove, a second dielectric layer positioned on the surface of the first dielectric layer and filling the first groove, a first groove formed between the second dielectric layer and the substrate and lower than the top of the second dielectric layer and the upper surface of the substrate, a fourth dielectric layer covering the inner wall of the first groove and filling part of the space of the first groove, the fourth dielectric layer also covering the second dielectric layer, and a load stack structure positioned on the fourth dielectric layer and above the top of the second dielectric layer.

Inventors

  • LAI HUIXIAN
  • FENG LIWEI

Assignees

  • 福建省晋华集成电路有限公司

Dates

Publication Date
20260512
Application Date
20220421

Claims (12)

  1. 1. A semiconductor memory structure, comprising: A substrate; at least one first trench located on the upper surface of the substrate; a first dielectric layer distributed along the inner wall of the first trench; the second dielectric layer is positioned on the surface of the first dielectric layer and fills the first groove; The top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate; A fourth dielectric layer covering the inner wall of the first groove and filling part of the space of the first groove, wherein the fourth dielectric layer also covers the second dielectric layer; A load stack structure is located on the fourth dielectric layer and above the top of the second dielectric layer.
  2. 2. The semiconductor memory structure of claim 1, further comprising: The metal filling layer is positioned in the first groove and fills part of the space in the first groove, and the fourth dielectric layer is positioned between the metal filling layer and the substrate and used for isolating the metal filling layer from being electrically connected with the substrate.
  3. 3. The semiconductor memory structure of claim 2, wherein a third dielectric layer is located over the top of the metal fill layer and within the first recess, filling the first recess.
  4. 4. The semiconductor memory structure of claim 1, wherein the second dielectric layer comprises a first sub-layer formed on a surface of the first dielectric layer and a second sub-layer formed on a surface of the first sub-layer and filling the first trench.
  5. 5. The semiconductor memory structure of claim 1, wherein the first dielectric layer comprises an oxide dielectric layer, and/or, The second dielectric layer includes a nitride dielectric layer.
  6. 6. The semiconductor memory structure of claim 4, wherein the first sub-layer comprises a nitride dielectric layer and the second sub-layer comprises an oxide dielectric layer.
  7. 7. The semiconductor memory structure of claim 2, further comprising a gate stack formed over a top of the substrate.
  8. 8. The semiconductor memory structure of claim 7, wherein the gate stack comprises at least a first polysilicon layer, a first conductive layer, and a first mask layer sequentially disposed upward in a direction perpendicular to the upper surface of the substrate, and/or, The load stacking structure comprises a second polysilicon layer, a second conductive layer and a second mask layer which are sequentially distributed upwards along the direction vertical to the upper surface of the substrate.
  9. 9. The semiconductor memory structure according to claim 8, wherein the metal filling layer is made of a same material as the first conductive layer and the second conductive layer.
  10. 10. The semiconductor memory structure of claim 1, wherein an edge corner of a top of the first trench is arcuate.
  11. 11. A method for fabricating a semiconductor memory structure, comprising the steps of: providing a substrate, wherein a first groove is formed on the upper surface of the substrate; Sequentially forming a first dielectric material layer and a second dielectric material layer along the inner wall of the first groove; Partially removing the first dielectric material layer and the second dielectric material layer, and respectively forming a first dielectric layer and a second dielectric layer correspondingly, wherein the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, so that a first groove is formed between the second dielectric layer and the substrate; forming a fourth dielectric layer on the inner wall of the first groove, wherein the fourth dielectric layer covers the inner wall of the first groove and fills part of the space of the first groove, and the fourth dielectric layer also covers the second dielectric layer; a load stack structure is formed on the fourth dielectric layer and over the top of the second dielectric layer.
  12. 12. The method of claim 11, further comprising the step of, after forming a fourth dielectric layer on the inner wall of the first recess: a metal filling layer is formed within the first recess to partially fill the first recess, and the fourth dielectric layer is partially located between the metal filling layer and the substrate.

Description

Semiconductor memory structure and preparation method thereof The present application is a divisional application, the application number of which is 202210427201.4, the application date of which is 2022, 04, 21, the entire contents of which are incorporated herein by reference. Technical Field The application relates to the field of semiconductor memory structures, in particular to a semiconductor memory structure and a preparation method thereof. Background In the production of semiconductor memories, it is generally necessary to form trenches in the substrate surface and fill the trenches with other material layers, and during the process of filling these material layers, undesirable grooves may occur in the substrate surface as shown in fig. 1. Referring to fig. 1, the trench in which the shallow trench isolation structure is located is sequentially filled with a first material layer 103, a second material layer 104 and a third material layer 105, wherein the top height of the first material layer 103 is lower than the surface height of the substrate 101 and lower than the top height of the second material layer 104, so that grooves 102 are formed between the second material layer 104 and the substrate 101, and the grooves 102 are difficult to be filled and leveled in the subsequent production process of the semiconductor memory, and collapse is likely to occur along with the accumulation of the material layers in the production process of the subsequent semiconductor memory, which affects the flatness of the semiconductor memory, thereby affecting the yield of the semiconductor memory. Disclosure of Invention In view of the above, the present application provides a semiconductor memory structure and a method for manufacturing the same, which can eliminate grooves occurring during the process of filling a trench with various material layers, and improve the yield of the semiconductor memory. The application provides a semiconductor memory structure which comprises a substrate, at least one first groove, a first dielectric layer, a second dielectric layer, a load stacking structure and a load stacking structure, wherein the first groove is arranged on the upper surface of the substrate, the first dielectric layer is distributed along the inner wall of the first groove, the second dielectric layer is arranged on the surface of the first dielectric layer and fills the first groove, the top of the first dielectric layer is lower than the top of the second dielectric layer and the upper surface of the substrate, a first groove is formed between the second dielectric layer and the substrate, the fourth dielectric layer covers the inner wall of the first groove and fills part of the space of the first groove, the fourth dielectric layer also covers the second dielectric layer, and the load stacking structure is arranged on the fourth dielectric layer and is arranged above the top of the second dielectric layer. Optionally, the semiconductor device further comprises a metal filling layer, wherein the metal filling layer is positioned in the first groove and fills part of the space in the first groove, and the fourth dielectric layer is positioned between the metal filling layer and the substrate and used for isolating the metal filling layer from being electrically connected with the substrate. Optionally, the metal filling layer further comprises a third dielectric layer which is positioned above the top of the metal filling layer and positioned in the first groove to fill the first groove. Optionally, the second dielectric layer includes a first sub-layer and a second sub-layer, the first sub-layer is formed on the surface of the first dielectric layer, and the second sub-layer is formed on the surface of the first sub-layer and fills the first trench. Optionally, the first dielectric layer comprises an oxide dielectric layer and/or the second dielectric layer comprises a nitride dielectric layer. Optionally, the first sub-layer comprises a nitride dielectric layer and the second sub-layer comprises an oxide dielectric layer. Optionally, the semiconductor device further comprises a grid stacking structure formed above the top of the substrate. Optionally, the gate stack structure at least comprises a first polysilicon layer, a first conductive layer and a first mask layer which are sequentially distributed upwards along a direction vertical to the upper surface of the substrate, and/or the load stack structure comprises a second polysilicon layer, a second conductive layer and a second mask layer which are sequentially distributed upwards along a direction vertical to the upper surface of the substrate. Optionally, the preparation material of the metal filling layer is the same as the preparation material of the first conductive layer and the second conductive layer. Optionally, the edge corner at the top of the first groove is arc-shaped. The application provides a preparation method of a semiconductor memor