CN-122028723-A - Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, wherein the method for manufacturing the semiconductor element mainly comprises the steps of firstly forming a first intermetallic dielectric layer on a substrate and a first metal interconnection line in the first intermetallic dielectric layer, then forming a contact pad on the first intermetallic dielectric layer, forming a protective layer on the contact pad, removing part of the protective layer and exposing the contact pad, carrying out a chip detection test on the contact pad, removing the contact pad to form a groove, forming a dielectric layer and completely filling the groove, and then forming a second metal interconnection line in the dielectric layer.

Inventors

• LIN JIANTING
• Lin Chuanlan
• LIN JUFU

Assignees

• 联华电子股份有限公司

Dates

Publication Date

20260512

Application Date

20241121

Priority Date

20241105

Claims (16)

1. 1. A method of fabricating a semiconductor device, comprising: Forming a contact pad on the substrate; forming a protective layer on a part of the contact pad; Chip probe testing is carried out on the contact pad; Removing the contact pad to form a groove, and A dielectric layer is formed in the recess.
2. 2. The method of claim 1, further comprising: Forming a first inter-metal dielectric layer on the substrate and a first inter-metal interconnect in the first inter-metal dielectric layer; Forming the contact pad on the first inter-metal dielectric layer; Forming the protective layer on the contact pad; removing a portion of the protective layer to expose the contact pad; performing the chip detection test; Removing the contact pad to form the groove; Forming the dielectric layer to completely fill the recess, and Forming a second metal interconnect in the dielectric layer.
3. 3. The method of claim 2, further comprising removing the contact pad and exposing the first metal interconnect.
4. 4. The method of claim 2, further comprising planarizing the dielectric layer after forming the dielectric layer in the recess.
5. 5. The method of claim 1, wherein the top surface of the protective layer is level with the top surface of the dielectric layer.
6. 6. The method of claim 1, wherein the recess comprises an inverted T-shape.
7. 7. A semiconductor device, comprising: a substrate including a first region and a second region; a first inter-metal dielectric layer disposed in the first region and the second region; a first metal interconnect disposed within the first inter-metal dielectric layer of the first region; a dielectric layer disposed on the first metal interconnect, wherein the dielectric layer comprises an inverted T shape, and And the protective layer is arranged on the first inter-metal dielectric layer and surrounds the dielectric layer.
8. 8. The semiconductor element of claim 7, further comprising: The first metal interconnection is arranged in the first inter-metal dielectric layer of the second area; A contact pad disposed on the first metal interconnect in the second region, and The protection layer is disposed on the first inter-metal dielectric layer and part of the contact pad.
9. 9. The semiconductor device of claim 7, wherein a top surface of said dielectric layer is level with a top surface of said protective layer.
10. 10. The semiconductor device as defined in claim 7, wherein the protective layer comprises an L-shape.
11. 11. The semiconductor device as defined in claim 7, wherein the dielectric layer and the protective layer comprise different materials.
12. 12. A semiconductor device, comprising: A first inter-metal dielectric layer disposed on the substrate; A first metal interconnect disposed within the first inter-metal dielectric layer; A contact pad disposed on the first metal interconnect; a dielectric layer disposed on the contact pad, and A passivation layer surrounding the contact pad and the dielectric layer.
13. 13. The semiconductor device of claim 12, wherein said contact pad top surface comprises a curved surface.
14. 14. The semiconductor device of claim 12, wherein the bottom surface of the dielectric layer comprises a curved surface.
15. 15. The semiconductor device of claim 12, wherein a top surface of said dielectric layer is level with a top surface of said protective layer.
16. 16. The semiconductor device as defined in claim 12, wherein the protective layer comprises an L-shape.

Description

Semiconductor element and manufacturing method thereof Technical Field The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for removing a contact pad after performing a chip probe test on the contact pad. Background The semiconductor industry has experienced rapid growth due to the continued increase in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density results from the continual decrease in minimum feature size (minimum feature size), which enables more smaller elements to be integrated into a given area. These smaller electronic components also require smaller packages that utilize smaller areas than previous packages. Some smaller types of packages for semiconductor devices include Quad Flat Package (QFP), pin grid array (PIN GRID ARRAY, PGA) packages, ball grid array (ball GRID ARRAY, BGA) packages, flip Chip (FC), three-dimensional integrated chip (3 DIC), wafer level package (WAFER LEVEL PACKAGE, WLP), and package on package (package on package, poP) devices, among others. Three-dimensional integrated chips provide increased integration density and other advantages, such as faster speeds and higher bandwidths, due to the reduced length of interconnect lines between stacked chips. However, many challenges remain to be addressed for three-dimensional integrated chip technology. Disclosure of Invention The invention discloses a method for manufacturing a semiconductor device, which mainly comprises the steps of firstly forming a first intermetallic dielectric layer on a substrate and a first metal interconnection line in the first intermetallic dielectric layer, then forming a contact pad on the first intermetallic dielectric layer, forming a protective layer on the contact pad, removing part of the protective layer and exposing the contact pad, performing a chip detection test on the contact pad, removing the contact pad to form a groove, forming a dielectric layer and completely filling the groove, and then forming a second metal interconnection line in the dielectric layer. In another embodiment of the present invention, a semiconductor device is disclosed, which mainly comprises a substrate including a first region and a second region, a first inter-metal dielectric layer disposed in the first region and the second region, a first metal interconnect disposed in the first inter-metal dielectric layer of the first region, a dielectric layer disposed on the first metal interconnect and a protective layer disposed on the first inter-metal dielectric layer and surrounding the dielectric layer, wherein the dielectric layer comprises an inverted T shape. In another embodiment of the present invention, a semiconductor device mainly includes a first inter-metal dielectric layer disposed on a substrate, a first metal interconnect disposed in the first inter-metal dielectric layer, a contact pad disposed on the first metal interconnect, a dielectric layer disposed on the contact pad, and a protective layer surrounding the contact pad and the dielectric layer. Drawings Fig. 1 to 6 are schematic views illustrating a method for fabricating a semiconductor device according to an embodiment of the invention; FIG. 7 is a schematic diagram of a semiconductor device according to an embodiment of the invention; Fig. 8 to 10 are schematic views illustrating a method for fabricating a semiconductor device according to an embodiment of the invention; fig. 11 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention. Symbol description 12 Substrate 14 Metal interconnect 16 Metal interconnect 18 Inter-metal dielectric layer 20 Contact pad 22 Protective layer 24 Groove 26 Dielectric layer 28 Inter-metal dielectric layer 30 Stop layer 32 Inter-metal dielectric layer 34 Stop layer 36 Metal interconnect 42 First region 44 Second region 46 Horizontal part 48 Vertical portion 50 Horizontal part Detailed Description Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. One skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications. It is noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structu