CN-122028725-A - Semiconductor structure and preparation method thereof

Abstract

The application relates to a semiconductor structure and a preparation method thereof, wherein the preparation method of the semiconductor structure comprises the steps of forming a plurality of grooves in a semiconductor substrate, forming an isolation material layer on one side of the semiconductor substrate, grinding the isolation material layer to remove the isolation material layer between the grooves, etching the ground isolation material layer to remove the isolation material layer in the groove, and simultaneously keeping the isolation material layer in the isolation groove to form a groove isolation structure, forming a plurality of gate structures in an active area, wherein the width difference of the plurality of gate structures is smaller than the channel length difference of a plurality of transistors corresponding to the plurality of gate structures, the plurality of gate structures comprise a first gate structure, and the first gate structure covers and fills the groove. The application can effectively reduce the control difficulty of the technological process and can improve the integration level of the device when a plurality of grid structures are formed simultaneously.

Inventors

• SONG FURAN
• LIU NAISHUO

Assignees

• 合肥晶合集成电路股份有限公司

Dates

Publication Date

20260512

Application Date

20260413

Claims (10)

1. 1. A method of fabricating a semiconductor structure, comprising: providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, wherein the plurality of trenches comprise isolation trenches and channel trenches, the isolation trenches divide the semiconductor substrate into a plurality of active regions, and the depth of the channel trenches is smaller than that of the isolation trenches; Forming an isolation material layer on one side of the semiconductor substrate, wherein the isolation material layer fills the plurality of grooves; Grinding the isolation material layer to remove the isolation material layer between the grooves; etching the ground isolation material layer to remove the isolation material layer in the trench groove, and keeping the isolation material layer in the isolation groove to form a trench isolation structure; and forming a plurality of gate structures in the active region, wherein the width difference of the plurality of gate structures is smaller than the channel length difference of a plurality of transistors corresponding to the plurality of gate structures, the plurality of gate structures comprise a first gate structure, and the first gate structure covers and fills the channel groove.
2. 2. The method of fabricating a semiconductor structure of claim 1, wherein forming a plurality of trenches in the semiconductor substrate comprises: Forming a patterned mask layer on one side of the semiconductor substrate, wherein the mask layer is provided with a first mask opening and a second mask opening; Forming a plurality of trenches by performing a first etching process for the semiconductor substrate based on the mask layer, wherein the isolation trench is formed based on the first mask opening and the channel trench is formed based on the second mask opening; The first mask opening penetrates through the mask layer, the depth of the second mask opening is smaller than the thickness of the mask layer, or the first mask opening and the second mask opening penetrate through the mask layer.
3. 3. The method of manufacturing a semiconductor structure according to claim 2, wherein forming a patterned mask layer on one side of the semiconductor substrate comprises: forming a mask material layer on one side of the semiconductor substrate; forming a patterned first photoresist layer on one side of the mask material layer far away from the semiconductor substrate, wherein the first photoresist layer is provided with a first photoresist opening and a second photoresist opening; Performing a second etching process on the mask material layer based on the first photoresist layer to form the mask layer, wherein in the mask layer, the first mask opening is formed based on the first photoresist opening, and the second mask opening is formed based on the second photoresist opening; The first photoresist opening penetrates through the first photoresist layer, the depth of the second photoresist opening is smaller than the thickness of the first photoresist layer, or the first photoresist opening and the second photoresist opening penetrate through the first photoresist layer.
4. 4. The method for manufacturing a semiconductor structure according to claim 2, wherein the performing a first etching process for the semiconductor substrate based on the mask layer, forming the plurality of trenches, comprises: Forming the channel grooves with different depths in the semiconductor substrate, and/or, And forming different numbers of channel grooves in the semiconductor substrate corresponding to different first gate structures.
5. 5. The method of claim 2, wherein the mask layer comprises a first repair layer, a first stop layer, and a first hard mask layer sequentially stacked on the semiconductor substrate, The forming an isolation material layer on one side of the semiconductor substrate comprises the following steps: Removing the first hard mask layer; forming a second repair layer on the side wall and the bottom of each groove; and forming the isolation material layer on the surface of the first stop layer and the surface of the second repair layer.
6. 6. The method of claim 5, wherein the polishing stops at the first stop layer when the isolation material layer is polished to remove the isolation material layer between the trenches; After the polishing the isolation material layer to remove the isolation material layer located between the trenches, the method further comprises: removing the first stop layer; And etching the ground isolation material layer to remove the isolation material layer in the trench groove, and keeping the isolation material layer in the isolation groove to form a trench isolation structure, wherein the method comprises the following steps: And removing the isolation material layer, the first repair layer and the second repair layer in the channel groove.
7. 7. The method of fabricating a semiconductor structure as defined in claim 1, wherein the spacer material layer in the trench has voids therein, And etching the ground isolation material layer to remove the isolation material layer in the trench, and before keeping the isolation material layer in the isolation trench to form a trench isolation structure, further comprising: And performing ion implantation on the active region to form a well region.
8. 8. The method of claim 1, wherein forming a plurality of gate structures in the active region comprises: Forming a plurality of pseudo gate structures in the active region, wherein the pseudo gate structures comprise a gate dielectric layer, a pseudo gate layer and side walls positioned on the side walls of the pseudo gate layer; Forming a passivation material layer covering the dummy gate structures and filling regions between the dummy gate structures; grinding the passivation material layer to expose the dummy gate layer; removing the pseudo gate layer; and forming a gate electrode of the gate structure in the removing area of the dummy gate layer.
9. 9. The method of claim 1, wherein the plurality of gate structures further comprises a second gate structure, the second gate structure being located in the active region outside the channel trench.
10. 10. A semiconductor structure, characterized in that it is formed by a method for manufacturing a semiconductor structure according to any one of claims 1-9.

Description

Semiconductor structure and preparation method thereof Technical Field The present application relates to the field of integrated circuits, and more particularly, to a semiconductor structure and a method for fabricating the same. Background In a semiconductor device product such as CMOS, a plurality of transistors having a plurality of threshold voltages are provided. When the threshold voltages of different transistors differ greatly, the design rules and the sizes of the grid structures of the transistors have great differences. When a plurality of grid structures with different sizes are prepared and formed simultaneously under the same technological process condition, the technological process is difficult to control, defects are easy to occur, and the yield is low. Meanwhile, for the design end, in the limited area of the same technical node, how to place more transistors has important influence on the production efficiency and the cost. Disclosure of Invention Based on the above, the application provides the semiconductor structure capable of effectively reducing the control difficulty of the technological process and improving the integration level of the device and the preparation method thereof. A method of fabricating a semiconductor structure, comprising: providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, wherein the plurality of trenches comprise isolation trenches and channel trenches, the isolation trenches divide the semiconductor substrate into a plurality of active regions, and the depth of the channel trenches is smaller than that of the isolation trenches; Forming an isolation material layer on one side of the semiconductor substrate, wherein the isolation material layer fills the plurality of grooves; Grinding the isolation material layer to remove the isolation material layer between the grooves; etching the ground isolation material layer to remove the isolation material layer in the trench groove, and keeping the isolation material layer in the isolation groove to form a trench isolation structure; and forming a plurality of gate structures in the active region, wherein the width difference of the plurality of gate structures is smaller than the channel length difference of a plurality of transistors corresponding to the plurality of gate structures, the plurality of gate structures comprise a first gate structure, and the first gate structure covers and fills the channel groove. In one embodiment, the forming a plurality of trenches in the semiconductor substrate includes: Forming a patterned mask layer on one side of the semiconductor substrate, wherein the mask layer is provided with a first mask opening and a second mask opening; Forming a plurality of trenches by performing a first etching process for the semiconductor substrate based on the mask layer, wherein the isolation trench is formed based on the first mask opening and the channel trench is formed based on the second mask opening; The first mask opening penetrates through the mask layer, the depth of the second mask opening is smaller than the thickness of the mask layer, or the first mask opening and the second mask opening penetrate through the mask layer. In one embodiment, the forming a patterned mask layer on one side of the semiconductor substrate includes: forming a mask material layer on one side of the semiconductor substrate; forming a patterned first photoresist layer on one side of the mask material layer far away from the semiconductor substrate, wherein the first photoresist layer is provided with a first photoresist opening and a second photoresist opening; Performing a second etching process on the mask material layer based on the first photoresist layer to form the mask layer, wherein in the mask layer, the first mask opening is formed based on the first photoresist opening, and the second mask opening is formed based on the second photoresist opening; The first photoresist opening penetrates through the first photoresist layer, the depth of the second photoresist opening is smaller than the thickness of the first photoresist layer, or the first photoresist opening and the second photoresist opening penetrate through the first photoresist layer. In one embodiment, the forming the plurality of trenches by performing a first etching process for the semiconductor substrate based on the mask layer includes: Forming the channel grooves with different depths in the semiconductor substrate, and/or, And forming different numbers of channel grooves in the semiconductor substrate corresponding to different first gate structures. In one embodiment, the mask layer comprises a first repair layer, a first stop layer and a first hard mask layer sequentially stacked on the semiconductor substrate, The forming an isolation material layer on one side of the semiconductor substrate comprises the following steps: Removing the first hard mask layer; forming a second repair la