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CN-122028726-A - Integrated circuit and electronic device

CN122028726ACN 122028726 ACN122028726 ACN 122028726ACN-122028726-A

Abstract

The embodiment of the application provides an integrated circuit and electronic equipment, and relates to the technical field of electronic equipment. The integrated circuit comprises a chip, a plurality of first connecting pieces, a first conductive group and a second conductive group. The chip is provided with a plurality of first through holes which are arranged at intervals, and the first through holes penetrate through the chip. The first connector is disposed in the first through hole. The first conductive group and the second conductive group are arranged on two sides of the chip, the first conductive group is electrically connected with one ends of the first connecting pieces, and the second conductive group is electrically connected with the other ends of the first connecting pieces. The first conductive group and/or the second conductive group comprises a plurality of conductive layers, a plurality of contact parts are arranged between two adjacent conductive layers, and the two adjacent conductive layers are electrically connected through the plurality of contact parts. The embodiment of the application can obtain the transmission path with large through-flow capacity without additionally increasing the preparation steps of the integrated circuit, and realize the signal transmission with excellent performance between the front surface and the back surface of the chip.

Inventors

  • LIU BINGYAO
  • ZHOU HAIFENG
  • LI YAOZHOU
  • HU YUYANG
  • XU YOU
  • ZENG QIULING

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260512
Application Date
20241105

Claims (14)

  1. 1. An integrated circuit, comprising: The chip is provided with a plurality of first through holes which are arranged at intervals, and the first through holes penetrate through the chip; a plurality of first connection members disposed in the first through holes; The first conductive groups and the second conductive groups are respectively arranged on two sides of the chip, the first conductive groups are electrically connected with one ends of the first connecting pieces, and the second conductive groups are electrically connected with the other ends of the first connecting pieces; The first conductive group and/or the second conductive group comprises a plurality of conductive layers which are stacked along a third direction and are arranged at intervals, the third direction is a direction perpendicular to the chip, a plurality of contact parts are arranged between two adjacent conductive layers, the contact parts are arranged at intervals along a direction parallel to the chip, and the two adjacent conductive layers are electrically connected through the contact parts.
  2. 2. The integrated circuit of claim 1, wherein at least one pair of contacts on a side surface of the different conductive layers adjacent to the chip and disposed adjacently are disposed in a stacked manner in the third direction.
  3. 3. The integrated circuit of claim 1 or 2, wherein the contact and the first connection are stacked in the third direction.
  4. 4. The integrated circuit of claim 1 or 2, wherein the number of the plurality of contacts between two adjacent conductive layers is greater than the number of the plurality of first connectors, wherein at least one contact is offset from the first connectors in the third direction.
  5. 5. The integrated circuit of any one of claims 1-4, wherein the chip comprises a substrate and a transistor, the substrate comprises a first surface and a second surface opposite in the third direction, and the transistor is disposed on the first surface; The integrated circuit further includes: a dielectric layer disposed on the first surface and surrounding the transistor; The second connectors are embedded in the dielectric layer, the second connectors and the first connectors are stacked in the third direction, and the first conductive group is electrically connected with the first connectors through the second connectors.
  6. 6. The integrated circuit of any one of claims 1-4, wherein the chip comprises a substrate and a transistor, the integrated circuit further comprising a dielectric layer and a plurality of second connectors; Wherein the first and second connectors stacked in the third direction are integrally provided.
  7. 7. The integrated circuit of any one of claims 1-6, further comprising: The transfer layer is arranged on one side, far away from the chip, of the second conductive group and is electrically connected with the second conductive group, and the thickness of the transfer layer is larger than that of the conductive layer and/or the width of the transfer layer is larger than that of the conductive layer.
  8. 8. The integrated circuit of any one of claims 1-7, wherein the chip comprises a substrate and a transistor, the transistor comprises an input-output transistor, a signal network of the input-output transistor is disposed on a side of the chip away from the second conductive group, and the first conductive group is electrically connected to the signal network of the input-output transistor.
  9. 9. The integrated circuit of claim 8, wherein the input-output transistor power supply network is disposed on a side of the chip remote from the first conductive group; The chip is also provided with a second through hole, and the input/output transistor is electrically connected with the power supply network through the second through hole; Wherein the size of the first through hole is the same as that of the second through hole.
  10. 10. The integrated circuit of claim 8 or 9, wherein the signal network of the input-output transistor comprises a plurality of signal layers, one of the plurality of signal layers of the first conductive group being disposed in common with a signal layer of the plurality of signal layers that is furthest from the chip, the one of the plurality of signal layers having a thickness that is greater than a thickness of a conductive layer of other of the plurality of signal layers.
  11. 11. The integrated circuit of any one of claims 1-10, wherein the chip comprises a substrate and a transistor, the transistor comprising a storage transistor, a power supply network of the storage transistor being disposed on a side of the chip remote from the second conductive group, the first conductive group being electrically connected to the power supply network of the storage transistor.
  12. 12. The integrated circuit of claim 11, wherein the chip comprises a plurality of memory transistors; the first conductive group is electrically connected with the storage transistors, and the corresponding plurality of first connecting pieces and second conductive groups are arranged on at least one side of the plurality of storage transistors along the direction parallel to the chip.
  13. 13. The integrated circuit of any one of claims 1-12, wherein the chip comprises a hot spot area, the hot spot area being an area of the chip having a higher temperature when in operation; The first through hole is formed in the hot spot area of the chip, and the first conductive group and the second conductive group corresponding to the hot spot area are in a floating state.
  14. 14. An electronic device, comprising: the integrated circuit of any one of claims 1-13; and the integrated circuit is arranged on the circuit board.

Description

Integrated circuit and electronic device Technical Field The present application relates to the field of electronic devices, and in particular, to an integrated circuit and an electronic device. Background Moore's law predicts the trend of integration density of transistors rising exponentially, with the evolution of the process, the current state-of-the-art devices have evolved to the nanometer scale. However, the miniaturization of the device size forces the metal line width to be synchronously compressed, and the resistance on the lead is obviously increased, so that the signal transmission delay and the power supply voltage drop are obviously increased, the improvement of the chip utilization rate and the reduction of the power consumption are limited, and the benefits of the power consumption, the performance, the area and the like of the advanced node are reduced. The backside supply network (backside power delivery, BSPDN) technology provides an effective solution to this problem, i.e. metal wires are added to the backside of the chip and connected to the devices on the front side of the chip through nano-vias (nTSV). Therefore, a power supply network can be constructed on the back metal, the front metal is completely used for signal wiring, on one hand, the voltage Drop (IR Drop) is obviously reduced by the thicker back metal network, and on the other hand, the winding pressure can be relieved by the winding resources released from the front, and the chip utilization rate or limit frequency is improved. However, in BSPDN technologies, after signals are generated and propagated on the front side of the chip, in order to facilitate subsequent packaging, a signal network on the front side of the chip still needs to be packaged with a packaging structure through a substrate arranged on the back side of the chip, and the current amplitude of some signals (such as input and output signals) is large, and in the process of transmitting the signals from the front side of the chip to the substrate on the back side of the chip, a transmission path with large through-flow capability is needed to be relied on to ensure that the signal transmission is better. Disclosure of Invention The embodiment of the application provides an integrated circuit and electronic equipment, and aims to obtain a transmission channel with large through-flow capacity and realize excellent signal transmission between the front surface and the back surface of a chip without additionally increasing the preparation steps of the integrated circuit and improving the preparation difficulty. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: in a first aspect, an integrated circuit is provided that includes a chip, a plurality of first connectors, a first conductive set, and a second conductive set. The chip is provided with a plurality of first through holes which are arranged at intervals, and the first through holes penetrate through the chip. The first connector is disposed in the first through hole. The first conductive group and the second conductive group are arranged on two sides of the chip, the first conductive group is electrically connected with one ends of the first connecting pieces, and the second conductive group is electrically connected with the other ends of the first connecting pieces. The first conductive group and/or the second conductive group comprises a plurality of conductive layers which are stacked along a third direction and are arranged at intervals, the third direction is a direction perpendicular to the chip, a plurality of contact parts are arranged between two adjacent conductive layers, the contact parts are arranged at intervals along a direction parallel to the chip, and the two adjacent conductive layers are electrically connected through the contact parts. In the integrated circuit provided by the embodiment of the application, the plurality of first connecting pieces are connected in parallel, and the plurality of layers of conductive layers in the first conductive group and/or the second conductive group connected by the first connecting pieces are connected in parallel, so that the overall resistance of the connecting assembly formed by the first conductive group, the second conductive group and the plurality of first connecting pieces interconnected between the first conductive group and the second conductive group is reduced, a transmission path (signal transmission with larger power supply amplitude) with large current capacity is obtained, and the reduction of resistance is realized without increasing the size of the first through hole where the first connecting piece is positioned, namely, the size of the first through hole can be the same as the size of the nano through hole nTSV, and the first through hole for signal transmission with larger current amplitude and the nano through hole nTSV for conventional signal transmission