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CN-122028727-A - Semiconductor device and method for manufacturing the same

CN122028727ACN 122028727 ACN122028727 ACN 122028727ACN-122028727-A

Abstract

The application relates to the technical field of semiconductor devices and discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a doped nitride-based semiconductor layer, at least one dielectric layer, at least one interconnection layer and a substrate connecting hole, wherein the epitaxial layer is positioned on the first surface of the substrate, the doped nitride-based semiconductor layer is positioned on one side, far away from the substrate, of the epitaxial layer, the doped nitride-based semiconductor layer comprises a first part, positioned in a sealing ring area, the at least one dielectric layer, the at least one interconnection layer penetrates through the epitaxial layer and the dielectric layer on the side, where the first surface of the substrate is positioned, of the substrate connecting hole and penetrates to the substrate, the at least one interconnection layer comprises a first interconnection block and a second interconnection block, the first interconnection block is positioned in the sealing ring area and is electrically connected with the first part, and the second interconnection block extends between the first interconnection block and the substrate connecting hole and electrically connects the first interconnection block with the substrate. According to the semiconductor device provided by the embodiment of the application, the film structure in the sealing ring region has both physical isolation function and electrical isolation function, so that the probability of electrical failure of the device is reduced.

Inventors

  • LI QING

Assignees

  • 英诺赛科(苏州)半导体有限公司

Dates

Publication Date
20260512
Application Date
20260410

Claims (10)

  1. 1. A semiconductor device having a device region and a seal ring region surrounding an outer periphery of the device region, the semiconductor device comprising: A substrate; An epitaxial layer on the first surface of the substrate, the epitaxial layer being for forming a two-dimensional electron gas in the device region parallel to the substrate; A doped nitride-based semiconductor layer located on a side of the epitaxial layer away from the substrate, the doped nitride-based semiconductor layer including a first portion located in the seal ring region, the first portion surrounding the device region, the first portion being configured to break the two-dimensional electron gas at a corresponding location; At least one dielectric layer positioned on one side of the epitaxial layer and the doped nitride-based semiconductor layer away from the substrate; at least one metal interconnection layer, at least part of which is positioned on one side of the dielectric layer away from the substrate; A substrate connecting hole located at one side of the sealing ring region, penetrating through the epitaxial layer and the dielectric layer at the side of the first surface of the substrate and penetrating to the substrate, The at least one metal interconnection layer comprises a first interconnection block and a second interconnection block, the first interconnection block is located in the sealing ring area and is electrically connected with the first part, and the second interconnection block extends between the first interconnection block and the substrate connection hole and electrically connects the first interconnection block with the substrate.
  2. 2. The semiconductor device of claim 1, wherein the first interconnect block and the second interconnect block are of unitary construction.
  3. 3. The semiconductor device of claim 1 or 2, wherein the at least one metal interconnect layer comprises a top metal interconnect layer furthest from the substrate, the first interconnect bump and the second interconnect bump being located at the top metal interconnect layer.
  4. 4. The semiconductor device of claim 1, wherein the substrate connection hole includes a groove provided recessed into the first surface, the second interconnect block extending to the groove.
  5. 5. The semiconductor device of claim 1, wherein the semiconductor device has a gate region in the device region, the doped nitride-based semiconductor layer further comprising a second portion located in the gate region, the semiconductor device further comprising: The gate metal layer comprises a gate metal block located in the gate region and a connecting metal block located in the sealing ring region, the gate metal block is located on one side, away from the substrate, of the second portion, and the connecting metal block is located on one side, away from the substrate, of the first portion.
  6. 6. A method of manufacturing a semiconductor device, comprising: Providing a substrate, wherein the substrate is provided with a device region and a sealing ring region surrounding the periphery of the device region; Forming an epitaxial layer on a first surface of a substrate, the epitaxial layer being used to form a two-dimensional electron gas in the device region parallel to the substrate; Forming a doped nitride-based semiconductor layer on one side of the epitaxial layer away from the substrate, wherein the doped nitride-based semiconductor layer comprises a first part positioned in the sealing ring region, the first part surrounds the device region, and the first part is used for cutting off the two-dimensional electron gas at a corresponding position; Forming at least one dielectric layer on one side of the epitaxial layer and the doped nitride-based semiconductor layer away from the substrate; Patterning the semiconductor device from the side of the first surface of the substrate to form a substrate connecting hole penetrating through the epitaxial layer and the dielectric layer and penetrating to the substrate, wherein the substrate connecting hole is positioned at one side of the sealing ring region; And forming at least one metal interconnection layer on one side of the epitaxial layer and the doped nitride-based semiconductor layer far away from the substrate, and forming a first interconnection block and a second interconnection block in the at least one metal interconnection layer, wherein at least part of the metal interconnection layer is positioned on one side of the dielectric layer far away from the substrate, the first interconnection block is positioned in the sealing ring region and is electrically connected with the first part, and the second interconnection block extends between the first interconnection block and the substrate connection hole and electrically connects the first interconnection block with the substrate.
  7. 7. The method of manufacturing a semiconductor device according to claim 6, wherein forming at least one metal interconnect layer on a side of the epitaxial layer and the doped nitride-based semiconductor layer away from the substrate, and forming a first interconnect block and a second interconnect block in the at least one metal interconnect layer, comprises: Forming a top metal interconnection layer on one side of the dielectric layer far away from the substrate; And patterning the top metal interconnection layer to obtain the first interconnection block and the second interconnection block.
  8. 8. The method of manufacturing a semiconductor device according to claim 6, wherein patterning the semiconductor device from a side of the first surface of the substrate to form a substrate connection hole penetrating the epitaxial layer and the dielectric layer and penetrating to the substrate, comprises: Performing first patterning on the semiconductor device from the side of the first surface of the substrate, and forming a first sub-hole penetrating through the dielectric layer at one side of the sealing ring region; and performing second patterning on the semiconductor device from the side of the first surface of the substrate to form a second sub-hole penetrating through the epitaxial layer, wherein the second sub-hole is communicated with the first sub-hole to form a substrate connecting hole.
  9. 9. The method of manufacturing a semiconductor device according to claim 6, wherein patterning the semiconductor device from a side of the first surface of the substrate to form a substrate connection hole penetrating the epitaxial layer and the dielectric layer and penetrating to the substrate, comprises: patterning the first surface of the substrate to form a groove recessed into the first surface.
  10. 10. The method for manufacturing a semiconductor device according to claim 6, further comprising: And forming a passivation layer on the side, away from the substrate, of the at least one metal interconnection layer.

Description

Semiconductor device and method for manufacturing the same Technical Field The present application relates to the field of semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the same. Background In a semiconductor device such as a high electron mobility transistor (High Electron Mobility Transistor, HEMT), a device region and a seal ring region surrounding the periphery of the device region are included. The seal ring region is provided with a seal ring formed by a plurality of film layers such as a metal interconnection layer and a dielectric layer of the semiconductor device. In the related art, the sealing ring of the semiconductor device is mainly used as a physical isolation structure, and when the ion implantation partition is cancelled in the area between the sealing ring area and the device area, at least part of the structure in the sealing ring of the related art has the possibility of electric leakage, so that the probability of electrical failure of the device is high. Disclosure of Invention The embodiment of the application provides a semiconductor device and a manufacturing method thereof, wherein in a structure that ion implantation partition is canceled in a region between a sealing ring region and a device region, a film layer structure in the sealing ring region has both a physical isolation function and an electrical isolation function, so that the probability of electrical failure of the device is reduced. In a first aspect, an embodiment of the present application provides a semiconductor device, where the semiconductor device has a device region and a sealing ring region surrounding the periphery of the device region, the semiconductor device includes a substrate, an epitaxial layer located on a first surface of the substrate, the epitaxial layer being configured to form a two-dimensional electron gas parallel to the substrate in the device region, a doped nitride-based semiconductor layer located on a side of the epitaxial layer away from the substrate, the doped nitride-based semiconductor layer including a first portion located in the sealing ring region, the first portion surrounding the device region, the first portion being configured to disconnect the two-dimensional electron gas at a corresponding location, at least one dielectric layer located on a side of the epitaxial layer and the doped nitride-based semiconductor layer away from the substrate, at least one metal interconnect layer located on a side of the dielectric layer away from the substrate, a substrate connection hole located on a side of the sealing ring region, the connection hole penetrating the substrate on a side of the first surface of the substrate, the first portion surrounding the device region, the first portion being configured to disconnect the two-dimensional electron gas at a corresponding location, at least one dielectric layer located on the epitaxial layer and the doped nitride-based semiconductor layer, and the doped nitride-based semiconductor layer being located on a side of the substrate, at least one metal interconnect layer located on a side of the substrate, and at least one dielectric interconnect layer located on a side of the dielectric layer, and at least one metal interconnect layer located on the side of the substrate. According to some of the foregoing embodiments of the first aspect of the present application, the first interconnect block and the second interconnect block are of unitary construction. According to some of the foregoing embodiments of the first aspect of the present application, the at least one metal interconnect layer includes a top metal interconnect layer furthest from the substrate, the first interconnect bump and the second interconnect bump being located at the top metal interconnect layer. According to some of the foregoing embodiments of the first aspect of the present application, the substrate connection hole includes a groove provided recessed into the first surface, and the second interconnect block extends to the groove. According to some of the foregoing embodiments of the first aspect of the present application, the semiconductor device has a gate region in the device region, the doped nitride-based semiconductor layer further includes a second portion located in the gate region, the semiconductor device further includes a gate metal layer including a gate metal block located in the gate region and a connection metal block located in the seal ring region, the gate metal block being located on a side of the second portion remote from the substrate, the connection metal block being located on a side of the first portion remote from the substrate. In a second aspect, an embodiment of the application provides a method for manufacturing a semiconductor device, which comprises the steps of providing a substrate, forming an epitaxial layer on a first surface of the substrate, wherein the epitaxial layer is use