CN-122028728-A - Depletion type gallium nitride field effect transistor

Abstract

The invention discloses a depletion type gallium nitride field effect transistor which comprises a group of gallium nitride transistor wafers, wherein each gallium nitride transistor wafer is provided with a drain electrode pad, a source electrode pad and a grid electrode pad, the group of gallium nitride transistor wafers are connected in parallel, the depletion type gallium nitride field effect transistor further comprises a silicon transistor wafer, the silicon transistor wafer is connected with the group of gallium nitride transistor wafers in parallel in a cascading manner, and the depletion type gallium nitride field effect transistor further comprises three or more than three packaging pads, wherein the packaging drain electrode pad is connected with the drain electrode pad on the group of two or more than two gallium nitride transistor wafers, the packaging source electrode pad is connected with the source electrode pad of the silicon transistor wafer, and the packaging grid electrode pad is connected with the grid electrode pad of the silicon transistor wafer. Optimizing the structure of the parallel depletion type gallium nitride field effect tube package, adding a package heat dissipation enhancement pad, balancing a heat dissipation structure, and expanding the power and the efficiency of the depletion type gallium nitride field effect tube.

Inventors

• ZHAO ZHENTAO

Assignees

• 摩驱科技(深圳)有限公司

Dates

Publication Date

20260512

Application Date

20250125

Claims (3)

1. 1. The depletion type gallium nitride field effect transistor is characterized by comprising two or more than two gallium nitride transistor wafers, wherein each gallium nitride transistor wafer is provided with a drain electrode pad, a source electrode pad and a grid electrode pad, the gallium nitride transistor wafers are connected in parallel, the drain electrode pad, the source electrode pad and the grid electrode pad which are arranged on the gallium nitride transistor wafers are respectively connected, the depletion type gallium nitride field effect transistor further comprises a silicon transistor wafer, the drain electrode pad, the source electrode pad and the grid electrode pad are arranged on the silicon transistor wafer, the drain electrode pad is connected with the source electrode pad of the gallium nitride transistor wafers, the source electrode pad is connected with the grid electrode pad of the gallium nitride transistor wafers, and the depletion type gallium nitride field effect transistor further comprises a package pad which is connected with the grid electrode pad of the gallium nitride transistor wafers, and a package pad which is connected with the grid electrode pad of the silicon transistor wafers.
2. 2. The depletion type gallium nitride field effect transistor of claim 1, further comprising a ceramic copper-clad plate gasket, wherein the ceramic copper-clad plate gasket is composed of a top metal layer, a ceramic substrate layer and a bottom metal layer, the top metal layer is connected with source pads of two or more than two gallium nitride transistor wafers, and the bottom metal layer of the ceramic copper-clad plate gasket is used as a packaging heat dissipation enhancement pad of a group of packaging pads.
3. 3. A depletion type GaN FET according to claim 1, wherein two or more of the GaN transistor wafers are replaced with a single wafer comprising two or more of the GaN transistor cells.

Description

Depletion type gallium nitride field effect transistor Technical Field The invention relates to a novel third-generation semiconductor cascade architecture design, and relates to a packaging process for a power device and optimization of a chip heat dissipation process and architecture design. Background With the advancement of technology, power devices are used in large numbers in electronic products. The third generation semiconductor material GaN (gallium nitride) is an outstanding representation of wide bandgap semiconductors. The forbidden band of GaN is 3 times that of Si (silicon), and the breakdown field is 10 times that of Si. Therefore, the power device manufactured by gallium nitride has the remarkable characteristics of high switching speed, low on-resistance, small chip area and the like, and is widely applied to the fields of power adapters, industrial power supplies, automobile electronics and the like. GaN (gallium nitride) power devices are generally classified into normally-on (depletion) and normally-off (enhancement) gallium nitride. The enhancement type GaN power device needs to be turned off under negative pressure, so that the enhancement type GaN power device is difficult to directly use in practical application. The depletion type GaN solution in the market at present is mainly synthesized by a depletion type GaN power device and a low-voltage Si MOSFET (field effect transistor) device, and the GaN power device can be flexibly matched with the low-voltage Si device in consumer electronics application, so that the application characteristics of high frequency and high conversion efficiency of GaN can be fully utilized, and the GaN power device can be fully compatible with the Si MOSFET in driving. At present, a plurality of cascaded single tubes are adopted for parallel connection of depletion type gallium nitride (GaN) field effect transistors (MOS tubes), two depletion type gallium nitride (GaN) field effect transistors are connected in parallel, and two depletion type gallium nitride transistors and two silicon field effect transistors respectively cascaded are connected in parallel. The ceramic copper-clad plate is composed of a ceramic substrate and one or two conductive layers, and can be directly bonded to the surface of the ceramic substrate by copper foil at high temperature, and has high heat conduction property. The sealed depletion type GaN field effect transistor has three poles, namely a drain electrode D, a source electrode S and a grid electrode G. The drain electrode D is from a gallium nitride transistor wafer, the source electrode S and the grid electrode are from a silicon transistor wafer, and therefore heat dissipation mainly depends on the drain electrode D from the gallium nitride transistor wafer and the source electrode S from the silicon transistor wafer, heat dissipation of the gallium nitride transistor wafer of a main heating part is not uniform enough, and the working efficiency of the depletion type GaN field effect transistor after integral packaging is affected. Disclosure of Invention In view of the above, the present invention is directed to providing a depletion type gallium nitride field effect transistor, in which a group of gallium nitride transistor wafers are cascaded with a single silicon transistor wafer, and the package heat dissipation enhancement pad connected with the source pad of the gallium nitride transistor wafer is added, and the power of the depletion type gallium nitride field effect transistor is expanded, so that the working efficiency of the depletion type gallium nitride field effect transistor is increased. In order to achieve the technical purpose, the scheme of the invention is that the depletion type gallium nitride field effect transistor comprises two or more than two gallium nitride transistor wafers, wherein each gallium nitride transistor wafer is provided with a drain electrode pad, a source electrode pad and a grid electrode pad, the gallium nitride transistor wafers are connected in parallel, the drain electrode pad, the source electrode pad and the grid electrode pad which are arranged on the gallium nitride transistor wafers are respectively connected, the depletion type gallium nitride field effect transistor further comprises a silicon transistor wafer, the drain electrode pad, the source electrode pad and the grid electrode pad are arranged on the silicon transistor wafer, the drain electrode pad is connected with the source electrode pad of one gallium nitride transistor wafer of two or more than two, the source electrode pad is connected with the grid electrode pad of one gallium nitride transistor wafer of two or more than two, the packaging pad comprises a packaging drain electrode pad, a packaging source electrode pad and a packaging grid electrode pad, the packaging drain electrode pad is connected with the drain electrode pad of one gallium nitride transistor wafer of two or more than two, the packagi