CN-122028741-A - Semiconductor device, manufacturing method thereof, chip and electronic equipment

Abstract

The embodiment of the application provides a semiconductor device, a preparation method thereof, a chip and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device comprises a substrate, a first dielectric layer, a first alignment mark, a conductive structure and a conductive structure, wherein the first groove is formed in the substrate, the first dielectric layer is arranged on the substrate, a second groove is formed in one side, far away from the substrate, of the first dielectric layer, the second groove is arranged corresponding to the first groove, the alignment mark is located in the second groove, the through silicon hole penetrates through the first dielectric layer and extends into the substrate, the conductive structure is filled in the through silicon hole, and the alignment mark and at least one part of the conductive structure are made of the same material and are arranged in the same layer. The alignment mark in the second groove has higher contrast and is easier to align and identify during exposure.

Inventors

• LIU YANG
• ZHAO NAN
• GUAN YONG
• LI HANG
• WU HOUYA

Assignees

• 华为技术有限公司

Dates

Publication Date

20260512

Application Date

20241104

Claims (14)

1. 1. A semiconductor device, comprising: A substrate, wherein a first groove is formed in the substrate; the first dielectric layer is arranged on the substrate, wherein a second groove is formed in one side, far away from the substrate, of the first dielectric layer, and the second groove is arranged corresponding to the first groove; the alignment mark is positioned in the second groove; the silicon through hole penetrates through the first dielectric layer and extends into the substrate; and the conductive structure is filled in the through silicon via, and the alignment mark and at least one part of the conductive structure are made of the same material and are arranged in the same layer.
2. 2. The semiconductor device of claim 1, wherein the conductive structure comprises a conductive pillar filled in the through silicon via, the alignment mark being the same material and disposed in the same layer as the conductive pillar.
3. 3. The semiconductor device of claim 1, wherein the conductive structure comprises a barrier layer and a conductive pillar, The conductive posts are filled in the through silicon vias; the barrier layer is arranged between the conductive column and the through silicon via; The alignment mark is the same as and is provided in the same layer as at least one of the conductive pillar and the barrier layer.
4. 4. The semiconductor device of claim 1, wherein the conductive structure comprises a barrier layer, a seed layer, and a conductive pillar, The conductive posts are filled in the through silicon vias; The seed layer is arranged between the conductive column and the through silicon via; the barrier layer is arranged between the seed layer and the through silicon via; the alignment mark is made of the same material and is arranged on the same layer as at least one of the conductive column, the seed layer and the barrier layer.
5. 5. The semiconductor device according to claim 3 or 4, wherein the material of the barrier layer comprises at least one or more of titanium, tantalum, titanium nitride, tantalum nitride.
6. 6. The semiconductor device of any of claims 1-5, wherein a side surface of the alignment mark remote from the substrate and a side surface of the first dielectric layer remote from the substrate are flush.
7. 7. The semiconductor device according to any one of claims 1 to 6, further comprising an insulating layer, The insulating layer is arranged between the through silicon via and the conductive structure and covers the side wall and the bottom wall of the through silicon via.
8. 8. The semiconductor device of any of claims 1-7, further comprising a second dielectric layer, The second dielectric layer covers the first dielectric layer, the alignment mark and the conductive structure.
9. 9. A method of manufacturing a semiconductor device, comprising: Forming a first groove on a substrate; Forming a first dielectric layer on the substrate, wherein a second groove is formed on one side, far away from the substrate, of the first dielectric layer, and the second groove is formed corresponding to the first groove; forming a through silicon via penetrating the first dielectric layer and extending into the substrate; and forming a conductive structure and an alignment mark, wherein the alignment mark is positioned in the second groove, the conductive structure is filled in the through silicon via, and the alignment mark is made of the same material and arranged in the same layer as at least one part of the conductive structure.
10. 10. The method of claim 9, wherein forming the conductive structure and the alignment mark comprises: forming a conductive layer, wherein the conductive layer covers the first dielectric layer, and part of the conductive layer is also filled in the through silicon via and the second groove; And flattening the conductive layer, reserving the part of the conductive layer filled in the through silicon via to obtain the conductive structure, and reserving the part of the conductive layer filled in the second groove to obtain the alignment mark.
11. 11. The method of claim 9, wherein the step of determining the position of the substrate comprises, The forming of the conductive structure and the alignment mark comprises: forming a barrier layer which covers the first dielectric layer, and filling part of the barrier layer into the through silicon via and the second groove; forming a conductive layer, wherein the conductive layer covers the barrier layer; And flattening the barrier layer and the conductive layer, retaining the conductive layer and the part of the barrier layer filled in the silicon through hole to obtain the conductive structure, and retaining at least the part of the barrier layer positioned in the second groove to obtain the alignment mark.
12. 12. The method of claim 9, wherein the step of determining the position of the substrate comprises, The forming of the conductive structure and the alignment mark comprises: forming a barrier layer which covers the first dielectric layer, and filling part of the barrier layer into the through silicon via and the second groove; Forming a seed layer, wherein the seed layer covers the barrier layer; forming a conductive layer, wherein the conductive layer covers the seed layer; And flattening the barrier layer, the seed layer and the conductive layer, retaining the conductive layer, the seed layer and the part of the barrier layer filled in the through silicon via to obtain the conductive structure, and retaining at least the part of the barrier layer positioned in the second groove to obtain the alignment mark.
13. 13. A chip comprising a substrate and the semiconductor device according to any one of claims 1-8, wherein the semiconductor device and the substrate are electrically connected.
14. 14. An electronic device comprising a printed circuit board and the chip of claim 13, wherein the chip and the printed circuit board are electrically connected.

Description

Semiconductor device, manufacturing method thereof, chip and electronic equipment Technical Field The embodiment of the application relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method of the semiconductor device, a chip and electronic equipment. Background In the chip preparation industry, alignment is required when a photoetching exposure process is carried out, so that the alignment deviation between a later exposure image layer and a previous image layer is ensured to meet the design standard. When the first layer pattern exposure is performed, alignment is not performed because of no alignment mark, and alignment is performed by using the alignment mark of the previous layer or layers when the subsequent layer pattern exposure is performed. The quality of the alignment mark not only influences whether the photoetching machine can correctly identify the mark pattern, but also influences the deviation precision of overlay. Disclosure of Invention The embodiment of the application provides a semiconductor device, a preparation method thereof, a chip and electronic equipment, which are used for improving the definition of an alignment mark and improving the alignment precision. In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme: The first aspect provides a semiconductor device, which comprises a substrate, a first dielectric layer, a second dielectric layer, an alignment mark, a through silicon via and a conductive structure, wherein the first groove is formed in the substrate, the first dielectric layer is arranged on the substrate, the second groove is formed in one side, far away from the substrate, of the first dielectric layer, the second groove is arranged corresponding to the first groove, the alignment mark is located in the second groove, the through silicon via penetrates through the first dielectric layer and extends into the substrate, the conductive structure is filled in the through silicon via, and the alignment mark and at least one part of the conductive structure are made of the same material and are arranged in the same layer. The semiconductor device provided by the embodiment of the application comprises a first groove formed on a substrate, and a second groove formed on the first dielectric layer due to shape retention. In the process of forming the conductive structure, an alignment mark is formed in the second groove, and the alignment mark has higher contrast, is easier to align and identify during exposure, and reduces the risk of alignment failure. And only the process of forming the conductive structure is utilized, no other additional process is needed, and the method has wide application prospect. In one possible embodiment, the conductive structure includes conductive pillars filled in the through silicon vias, and the alignment marks are of the same material and are provided in the same layer as the conductive pillars. In one possible embodiment, the conductive structure includes a barrier layer and a conductive pillar filled in the through silicon via, the barrier layer is disposed between the conductive pillar and the through silicon via, and the alignment mark is the same material and is disposed in the same layer as at least one of the conductive pillar and the barrier layer. In one possible embodiment, the conductive structure includes a barrier layer, a seed layer, and a conductive pillar filled in the through-silicon via, the seed layer is disposed between the conductive pillar and the through-silicon via, the barrier layer is disposed between the seed layer and the through-silicon via, and the alignment mark is the same material and is disposed in the same layer as at least one of the conductive pillar, the seed layer, and the barrier layer. In one possible embodiment, the material of the barrier layer comprises at least one or a combination of titanium, tantalum, titanium nitride, tantalum nitride. Therefore, the barrier layer can prevent the diffusion of the metal material to silicon or other materials in the high-temperature treatment or processing process, and the stability and the integrity of the circuit are maintained. And the material of the blocking layer has higher contrast and is easier to align and identify during exposure. In one possible embodiment, the alignment mark is flush with a side surface of the first dielectric layer remote from the substrate. In one possible embodiment, the semiconductor device further comprises an insulating layer disposed between the through-silicon via and the conductive structure and covering the sidewall and the bottom wall of the through-silicon via. In one possible embodiment, the semiconductor device further includes a second dielectric layer covering the first dielectric layer, the alignment mark, and the conductive structure. The second aspect provides a method for manufacturing a semiconduct