CN-122028742-A - Wafer, manufacturing method of wafer, chip and electronic equipment

Abstract

The embodiment of the application provides a wafer, a manufacturing method of the wafer, a chip and electronic equipment. The wafer includes a dielectric element, a passivation layer, and a first crack guide structure. The passivation layer is arranged on the dielectric unit. The medium unit area is divided into a functional area and a cutting channel. The peripheral side of the functional area is provided with a cutting channel. The dielectric unit includes a dielectric stack disposed in a stack on a substrate. The dielectric stack includes a first dielectric layer and a second dielectric layer overlying the first dielectric layer. A first crack guide structure is located between the functional area and the scribe line, the first crack guide structure comprising a multi-interface structure. The multi-interface structure is blocked between adjacent dielectric stacks and is configured to be capable of guiding crack propagation toward a side where the passivation layer is located. The wafer provided by the embodiment of the application has the advantages that through the arrangement of the multi-interface structure, the chip failure caused by layering of the wafer in the cutting process is avoided, the yield of the chip can be improved, and the size of the chip is not influenced.

Inventors

• LI MEIXIAN
• WANG LIYING

Assignees

• 荣耀终端股份有限公司

Dates

Publication Date

20260512

Application Date

20241104

Claims (20)

1. 1. A wafer, comprising: A substrate; The medium unit is overlapped on the substrate and is divided into a functional area and a cutting channel in a region, and the cutting channel is arranged on the periphery of the functional area; the dielectric unit comprises at least two dielectric stacks stacked on the substrate, wherein the dielectric stacks comprise a first dielectric layer and a second dielectric layer, and the second dielectric stack is arranged on the first dielectric layer; defining one of two adjacent dielectric stacks adjacent to one side of the substrate as a lower dielectric stack, and defining one of two adjacent dielectric stacks adjacent to one side of the passivation layer as an upper dielectric stack, wherein part of the first dielectric layer in the upper dielectric stack is embedded in the first dielectric layer in the lower dielectric stack; The passivation layer is overlapped on one surface of the medium unit, which is away from the substrate; crack guide apparatus comprising a first crack guide structure located between the functional region and the dicing street, the first crack guide structure comprising a multi-interface structure blocked between adjacent ones of the dielectric stacks and configured to be capable of guiding the crack to propagate towards a side where the passivation layer is located.
2. 2. The wafer of claim 1, wherein the first dielectric layer and the second dielectric layer are of different materials, and the material of the multi-interface structure is the same as the material of the second dielectric layer.
3. 3. The wafer of claim 1 or 2, wherein the first dielectric layer of the dielectric stack is facing the substrate, the first dielectric layer and the second dielectric layer are of a different material than the substrate, wherein the first dielectric layer is of a glass or semiconductor material and the second dielectric layer is of a lithographically and antireflective material.
4. 4. The wafer of any of claims 1-3, wherein the first dielectric layer in the upper dielectric stack has a first protrusion on a side facing the substrate, the first protrusion being embedded in the first dielectric layer in the lower dielectric stack and being blocked from the lower dielectric stack by a first interfacial layer; The first crack guide structure comprises the first protruding portion, the multi-interface structure comprises the first interface layer, one end of the first interface layer, facing the substrate, is connected with the other medium laminated layer, and forms a first stress concentration portion, and the first stress concentration portion is configured to enable the crack to be forced to expand along the first interface layer towards one side where the passivation layer is located.
5. 5. The wafer of claim 4, wherein two adjacent dielectric stacks together define a receiving groove at a position corresponding to the first protrusion, a notch of the receiving groove faces the passivation layer, and a groove wall of the receiving groove is surrounded by the second dielectric layer; the material of the first dielectric layer in the other dielectric layer stack of the notch is filled in the accommodating groove to form the first bulge part, the part of the second dielectric layer corresponding to the groove side wall of the accommodating groove forms the first interface layer, and one end of the first interface layer connected with the groove bottom wall of the accommodating groove forms the first stress concentration part; the first stress riser is configured to force the crack to propagate along the first interface layer to the notch.
6. 6. The wafer of claim 5, wherein the first dielectric layer in the upper dielectric stack is further overlapped at a position corresponding to the notch of the second dielectric layer in the lower dielectric stack, the overlapped portion of the second dielectric layer in the lower dielectric stack and the portion corresponding to the bottom wall of the accommodating groove form a second interface layer together, the first interface layers in two adjacent accommodating grooves are connected by the second interface layer along the stacking direction of the dielectric stack, and the multi-interface structure further comprises the second interface layer.
7. 7. The wafer of claim 5 or 6, wherein the receiving groove is located on a side of the functional area facing the dicing street and surrounds at least a portion of the circumference of the functional area.
8. 8. The wafer of claim 7, wherein the receiving groove is an annular groove, and/or, The accommodating groove comprises a plurality of independent groove sections, and the groove sections are arranged at intervals along the circumferential direction of the functional area.
9. 9. The wafer of any one of claims 5-8, wherein the passivation layer is provided with a second bump and a crack exit, both located between the functional region and the scribe line, the second bump being located in the pocket defined by two adjacent stacks of media, the crack exit being located laterally of the second bump and extending through the passivation layer, the first crack guide structure further comprising the second bump and the crack exit; The multi-interface structure is also blocked between the second protrusion and an adjacent media stack and is configured to be capable of guiding the crack to propagate toward the crack exit.
10. 10. The wafer of claim 9, wherein portions of the passivation layer further overlap adjacent the dielectric stack at locations corresponding to the notches, the second dielectric layer in the dielectric stack forming a third interface layer at portions corresponding to the portions overlapped by the passivation layer and the crack exits; The multi-interface structure further comprises a third interface layer, and the third interface layer is connected with the first interface layer in the accommodating groove where the second protruding part is located.
11. 11. The wafer of claim 10, wherein an inner wall of the crack vent meets the third interface layer, the location where the inner wall of the crack vent meets the third interface layer forming a second stress riser; the second stress riser is configured to alter a propagation path of the crack on the third interface layer such that the crack propagates along an inner wall of the crack exit to a side of the passivation layer facing away from the dielectric unit.
12. 12. The wafer of any one of claims 9 to 11, wherein one of two adjacent ones of the accommodating cavities adjacent to the substrate is a lower accommodating cavity and one of the accommodating cavities adjacent to the passivation layer is an upper accommodating cavity defined along a stacking direction of the dielectric stack; The projection of the lower accommodating groove on the substrate is a first projection, the projection of the upper accommodating groove on the substrate is a second projection, and the second projection is positioned on one side of the first projection facing the cutting path and is spaced from the first projection.
13. 13. The wafer of claim 12, wherein the projection of the crack exit onto the substrate is a third projection, the third projection being located on a side of the second projection toward the scribe line with a spacing from the second projection.
14. 14. The wafer of claim 12 or 13, wherein the crack guide apparatus further comprises: And the second crack guiding structure is positioned on one side of the first crack guiding structure facing the functional area, is identical to the first crack guiding structure in structure and forms the crack guiding device together with the first crack guiding structure.
15. 15. The wafer of claim 14, wherein two crack guides are symmetrically disposed between the functional area and the scribe line.
16. 16. The wafer of any one of claims 9 to 11, wherein two adjacent dielectric stacks together define a plurality of said pockets, at least some of the pockets defined by two adjacent dielectric stacks are in communication with one another to form a network, and wherein the first interface layers of the plurality of pockets are in communication with one another to form a network interface.
17. 17. The wafer of claim 16, wherein the placement of the pockets within two of the dielectric stacks adjacent to the same dielectric stack is the same.
18. 18. The wafer of any one of claims 1-17, further comprising: The sealing ring is arranged on the periphery of the functional area in a surrounding manner and positioned between the functional area and the cutting channel, and comprises a plurality of sealing parts and a plurality of conducting parts, wherein the conducting parts and the sealing parts are alternately arranged in the corresponding dielectric stacks along the stacking direction of the dielectric stacks, and two adjacent sealing parts are interconnected through the conducting parts; wherein the crack guide device is arranged between the sealing ring and the cutting channel.
19. 19. A method of manufacturing a wafer according to any one of claims 1 to 18, the method comprising: a dielectric stack layer is stacked on the substrate, the dielectric stack layer comprises a first dielectric layer and a second dielectric layer, and the second dielectric layer is stacked on the first dielectric layer; Continuing to stack the dielectric stack layers on the substrate so that part of the first dielectric layers in the dielectric stack layers stacked later are embedded in the first dielectric layers in the dielectric stack layers stacked earlier, forming dielectric units by the dielectric stack layers stacked mutually, wherein each dielectric unit is provided with a cutting channel and a functional area, and the periphery of each functional area is provided with the cutting channel; a passivation layer is stacked on the dielectric unit, wherein the multi-interface structure is configured to guide the crack to propagate toward a side where the passivation layer is located.
20. 20. The method of claim 19, wherein, Continuing to stack the dielectric stack on the substrate, so that part of the first dielectric layer in the dielectric stack stacked later is embedded in the first dielectric layer in the dielectric stack stacked earlier, wherein the step of stacking the dielectric stack on the substrate includes: Forming a containing groove in the first dielectric layer of the dielectric stack, wherein the containing groove is positioned between the functional area and the cutting channel, and a notch of the containing groove faces the passivation layer; continuing to stack the dielectric stacks so that the material of the first dielectric layer in the dielectric stack stacked later is filled in the accommodating groove to form a first protruding part on the first dielectric layer in the dielectric stack stacked later, wherein the first protruding part is embedded in the first dielectric layer in the dielectric stack stacked earlier; the multi-interface structure comprises a first interface layer, a second interface layer, a first protrusion part and a lower medium lamination layer, wherein the first interface layer is formed on the side wall of the accommodating groove, the first protrusion part is separated from the lower medium lamination layer through the first interface layer, and the multi-interface structure comprises the first interface layer.

Description

Wafer, manufacturing method of wafer, chip and electronic equipment Technical Field The present application relates to the field of chip technologies, and in particular, to a wafer, a method for manufacturing the wafer, a chip, and an electronic device. Background Currently, chips have been widely used in various electronic devices. The wafer has a functional area and dicing channels, and the peripheral side of the functional area is provided with dicing channels. When the wafer is cut along one edge of the dicing street, the chip can be obtained after the part of the wafer containing one of the functional areas is separated from the rest of the functional areas of the wafer. Wafers typically include a substrate and a dielectric element. The dielectric unit comprises a first dielectric layer and a second dielectric layer which are alternately stacked on a substrate. A second dielectric layer is arranged between the adjacent first dielectric layers, and the second dielectric layer can be regarded as an interface layer between the adjacent first dielectric layers. In the conventional wafer dicing process, delamination of the wafer between adjacent first dielectric layers is easily generated. If the layering extends to the functional area along the interface layer between adjacent first dielectric layers, it may cause the chip to fail. How to avoid the chip failure caused by dicing of the wafer has become a technical problem to be solved. Disclosure of Invention The application provides a wafer, a manufacturing method of the wafer, a chip and electronic equipment, which can avoid the chip failure caused by layering of the wafer in the cutting process, can improve the yield of the chip, and can not influence the size of the chip. In a first aspect, an embodiment of the present application provides a wafer. The wafer comprises: A substrate; The device comprises a substrate, a dielectric unit, a dielectric layer, a passivation layer, a first dielectric layer and a second dielectric layer, wherein the dielectric unit is overlapped on the substrate and is divided into a functional area and a cutting channel on the area, and the cutting channel is arranged on the periphery of the functional area; The passivation layer is overlapped on one surface of the medium unit, which is away from the substrate; a crack guide apparatus comprising a first crack guide structure located between a functional region and a scribe line, the first crack guide structure comprising a multi-interface structure that is blocked between adjacent dielectric stacks and configured to be capable of guiding crack propagation toward a side where a passivation layer is located. According to the embodiment of the application, through the arrangement of the multi-interface structure, when the crack in the medium unit is expanded to the multi-interface structure along the horizontal direction, the multi-interface structure can change the expansion direction of the crack, so that the expansion path of the crack is forced to change and deflect, and the crack is expanded towards one side where the passivation layer is positioned along the multi-interface structure, thereby avoiding the functional area layering and chip failure of the wafer caused by the fact that the crack is directly expanded to the functional area along the horizontal direction in the cutting process of the wafer, and improving the yield of the chip. Meanwhile, the complexity of the expansion path of the crack can be increased due to the arrangement of the multi-interface structure, so that more energy can be consumed when the crack expands along the multi-interface structure, and the expansion speed of the crack can be slowed down. The first crack guiding structure is located between the functional area and the cutting channel, so that the wafer can effectively utilize the area between the functional area and the cutting channel, and the size of a chip is not affected while the first crack guiding structure is arranged in the wafer. In some embodiments, the first dielectric layer and the second dielectric layer are of different materials, and the material of the multi-interface structure is the same as the material of the second dielectric layer. So configured, the multi-interface structure is capable of inhibiting crack propagation through a variety of inhibition mechanisms. These inhibition mechanisms include altering the crack propagation path to deflect the crack propagation path, increasing the complexity of the crack propagation path, slowing the crack propagation speed, passivating the crack tip, altering the crack tip stress, etc. The crack growth along the multi-interface structure can be better controlled by the combined action of the inhibition mechanisms, and the crack growth is effectively inhibited. In addition, the multi-interface structure can be formed by processing the wafer in the process of manufacturing the medium unit by utilizing the existing back-end process of