CN-122028747-A - Integrated circuit chip package without using lead frame

Abstract

Embodiments of the present disclosure relate to an integrated circuit chip package that does not utilize a lead frame. An integrated circuit die includes a semiconductor substrate, an interconnect layer including a bond pad, and a passivation layer covering the interconnect layer and including an opening at the bond pad. The passivation layer supports a conductive redistribution layer including conductive lines and conductive vias. An insulating layer covers the conductive redistribution layer and the passivation layer. The trench formed in the upper surface of the insulating layer defines a pedestal region in the insulating layer. A via extends from the upper surface of each base region through the base region and the insulating layer to reach and contact a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each base region in contact with its associated via. Metal pads are used for leads of quad flat no-lead (QFN) packages.

Inventors

• LUAN JINGEN

Assignees

• 意法半导体有限公司

Dates

Publication Date

20260512

Application Date

20230120

Priority Date

20221214

Claims (8)

1. 1. A method for forming a leadless integrated circuit package, comprising: Forming a conductive redistribution layer on an upper surface of a passivation layer of an integrated circuit including a plurality of bond pads; Covering the conductive redistribution layer with an insulating layer; Covering the insulating layer with a metal layer; forming an opening extending through the metal layer and the insulating layer to reach the conductive redistribution layer; forming a via in the opening in contact with the conductive redistribution layer; patterning the metal layer to form a metal pad in contact with the via hole, and Portions of the insulating layer not covered by the patterned metal layer are removed to define a base region of the insulating layer at the metal pad.
2. 2. The method of claim 1, wherein the insulating layer is made of a resin material.
3. 3. The method of claim 1, wherein forming the via comprises plating metal in the opening.
4. 4. The method of claim 1, wherein removing portions of the insulating layer comprises forming channels in the insulating layer to define the pedestal region.
5. 5. The method of claim 4, wherein the channel has a depth less than a thickness of the insulating layer.
6. 6. The method of claim 1, further encapsulating the integrated circuit in an encapsulant.
7. 7. The method of claim 1, further comprising a protective layer on a back side of the semiconductor substrate.
8. 8. The method of claim 1, wherein the integrated circuit package is a quad flat no-lead QFN type package.

Description

Integrated circuit chip package without using lead frame Description of the division The application is a divisional application of patent application of 2023, 01, 20, 202310055889.2 and entitled "integrated circuit chip package without leadframe". Cross Reference to Related Applications The present application claims priority from U.S. provisional patent application No. 63/304,087 filed on day 28, 1, 2022, the disclosure of which is incorporated herein by reference. Technical Field The present invention relates generally to packaging of integrated circuit chips, and more particularly to packaging of integrated circuit chips without the use of a leadframe. Background Referring to fig. 1, a cross-section of a conventional integrated circuit package 10, for example, of the quad flat no-lead (QFN) type, is shown. The lead frame 12, which is made of copper, for example, includes a die pad 12a and a plurality of leads 12b extending outwardly from the die pad 12 a. An integrated circuit die 16 is mounted to the upper surface of the die pad 12a using an adhesive material. The integrated circuit die 16 includes a semiconductor (e.g., silicon) substrate 16a and an interconnect layer 16b extending over the substrate 16 a. Substrate 16a supports a plurality of integrated circuit devices, such as transistors. The interconnect layer 16b includes a plurality of metallization layers supporting interconnect lines and interconnect vias, and a plurality of bond pads 16c. Bond wire 18 electrically connects bond pad 16c to lead 12b. An encapsulant 20 encapsulates the leadframe 12, the integrated circuit die 16, and the bond wires 18. Disclosure of Invention In one embodiment, a leadless integrated circuit package includes an integrated circuit die including a semiconductor substrate having a front side, an interconnect layer extending over the front side of the semiconductor substrate, wherein the interconnect layer includes a plurality of bond pads, and a passivation layer covering an upper surface of the interconnect layer and including openings at the bond pads, a conductive redistribution layer supported by the upper surface of the passivation layer, the conductive redistribution layer including wires extending over the passivation layer and conductive vias extending through the openings in the passivation layer to contact the bond pads, an insulating layer covering the conductive redistribution layer and the passivation layer, wherein the insulating layer includes a plurality of channels formed in an upper surface thereof to define a plurality of base regions in the insulating layer, vias extending from the upper surface of the base region through the base region and the insulating layer to reach and contact a portion of the conductive redistribution layer, and metal pads formed at the upper surface of the base region and in contact with the vias. In one embodiment, a method for forming a leadless integrated circuit package includes providing an integrated circuit comprising a semiconductor substrate having a front side, an interconnect layer extending over the front side of the semiconductor substrate, wherein the interconnect layer comprises a plurality of bond pads, and a passivation layer covering an upper surface of the interconnect layer and comprising openings at the bond pads, forming a conductive redistribution layer supported by the upper surface of the passivation layer, the conductive redistribution layer comprising wires extending over the passivation layer and conductive vias extending through the openings in the passivation layer to contact the bond pads, laminating a stack comprising an insulating layer and a metal layer over the conductive redistribution layer, forming a plurality of openings in the metal layer, extending the plurality of openings through the insulating layer to reach the conductive redistribution layer, electroplating to fill the plurality of openings with metal to form the vias, patterning the metal layer to form a plurality of metal pads in contact with the vias, and forming a plurality of channels in the insulating layer to define a base region of the insulating layer at each metal pad. In one embodiment, a leadless integrated circuit package comprises an integrated circuit die having a front surface comprising a plurality of bond pads and a passivation layer, a conductive redistribution layer over and electrically connected to the plurality of bond pads, an insulating layer over the conductive redistribution layer, wherein the insulating layer comprises a plurality of channels defining a plurality of base regions, a via extending through each base region to reach and contact the conductive redistribution layer, and a metal pad at an upper surface of each base region and in contact with the via thereof. In one embodiment, a leadless integrated circuit package comprises an integrated circuit die having a front surface comprising a plurality of bond pads and a passivation layer, an enca