CN-122028750-A - Substrate package

Abstract

A substrate package and a method of manufacturing the same are provided herein. The substrate package includes a carrier, a substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier, a non-conductive first barrier wall extending from the second major surface toward the carrier, the first barrier wall defining a first region and a second region of the substrate package, and a ball grid array including a plurality of solder balls between the substrate and the carrier, wherein a first subset of the solder balls are located within the first region and a second subset of the solder balls are located within the second region.

Inventors

• LIU HUANHUAN
• SUN YONGQING
• ZANG YUAN
• LI YIMING

Assignees

• 恩智浦美国有限公司

Dates

Publication Date

20260512

Application Date

20241104

Claims (10)

1. 1. A substrate package, comprising: A carrier; A substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier; a non-conductive first barrier wall extending from the second major surface toward the carrier, the first barrier wall defining a first region and a second region of the substrate package, and A ball grid array comprising a plurality of solder balls between the substrate and the carrier, wherein a first subset of the solder balls are located within the first region and a second subset of the solder balls are located within the second region.
2. 2. The substrate package of claim 1, wherein the first barrier wall extends from the second major surface to the carrier.
3. 3. The substrate package of claim 1, wherein the first barrier wall extends across a full width of the substrate package.
4. 4. The substrate package of claim 1, further comprising non-conductive second and third barrier walls at opposite ends of the substrate package to further define the first and second regions.
5. 5. The substrate package of claim 1, wherein the first barrier wall has a thickness greater than a diameter of the solder balls.
6. 6. A method of manufacturing a substrate package, the method comprising: forming a ball grid array comprising a plurality of solder balls distributed over a substrate in a first region and a second region, wherein a first subset of the solder balls are located within the first region and a second subset of the solder balls are located within the second region; forming a first non-conductive barrier wall on the substrate between the first region and the second region, and The substrate including the solder balls and the first barrier walls is mounted to a carrier to form the substrate package.
7. 7. The method of claim 6, further comprising forming non-conductive second and third barrier walls perpendicular to the first barrier wall and at two opposite ends of the substrate package.
8. 8. The method of claim 6, wherein the first barrier wall forms a seal with the carrier when the substrate package is formed.
9. 9. The method of claim 6, further comprising curing the first barrier wall.
10. 10. The method of claim 6, further comprising forming the first barrier wall from an epoxy material.

Description

Substrate package Technical Field The present disclosure relates to a substrate package. In particular, the present disclosure relates to a substrate package including a ball grid array with electrical isolation and a method of manufacturing the same. Background Ball grid array, BGA, is one type of surface mount package used in integrated circuits. In order to ensure safety and reliability, the gap distance and creepage distance need to be considered, for example, to prevent electrical breakdown and short circuits. The void distance refers to the shortest distance through air between two conductive portions or between a conductive portion of the device and a grounded surface. It is a measure of the insulating ability to withstand electrical stress without breakdown. The creepage distance is the shortest path along the surface of the insulating material between two conductive parts or between a conductive part of the device and the ground surface. This distance helps to prevent surface leakage currents that occur due to contamination, moisture, or other environmental factors. In order to meet the requirements of the gap distance and the creepage distance, the package size may become larger, especially in the high voltage domain. Reducing BGA balls can help manage creepage, however, imbalance in distribution can cause additional problems with ball level reliability. Disclosure of Invention According to a first aspect, a substrate package is provided. The substrate package includes a carrier, a substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier, a non-conductive first barrier wall extending from the second major surface toward the carrier, the first barrier wall defining a first region and a second region of the substrate package, and a ball grid array including a plurality of solder balls between the substrate and the carrier, wherein a first subset of the solder balls are located within the first region and a second subset of the solder balls are located within the second region. In some embodiments, the first barrier wall may extend from the second major surface to the carrier. The carrier comprises a printed circuit board, PCB, comprising a solder resist layer such that the first barrier wall extends a complete distance between the substrate and the carrier. In some embodiments, the first barrier wall extends across a full width of the substrate package. For example, to completely isolate the first region from the second region along the width of the substrate package. In some embodiments, the substrate package may additionally include non-conductive second and third barrier walls at opposite ends of the substrate package to further define the first and second regions. The second barrier wall and the third barrier wall are located at or near the periphery of the substrate package. In some embodiments, the second barrier wall and the third barrier wall may extend from the second major surface to the carrier. In some embodiments, the second barrier wall and the third barrier wall may be perpendicular to the first barrier wall. In some embodiments, the second barrier wall and the third barrier wall may extend across a full length of the substrate package. The length of the substrate package may be similar in size to the width of the substrate package. In some embodiments, the first region corresponds to a first voltage domain and the second region corresponds to a second voltage domain. In some embodiments, the first region has a larger surface area than the second region. In some embodiments, the first barrier wall comprises a plurality of walls. In some embodiments, the barrier wall (e.g., the first barrier wall or the first, second, and third barrier walls) has a thickness that is greater than the diameter of the solder balls. In some embodiments, the barrier walls (e.g., the first barrier wall or the first, second, and third barrier walls) form a seal between the substrate and the carrier. In some embodiments, wherein the barrier wall (e.g., the first barrier wall or the first, second, and third barrier walls) is made of an epoxy material. According to a second aspect, a method of manufacturing a substrate package is provided. The method includes forming a ball grid array including a plurality of solder balls distributed over a substrate in a first region and a second region, wherein a first subset of the solder balls are located within the first region and a second subset of the solder balls are located within the second region, forming a first barrier wall that is non-conductive over the substrate between the first region and the second region, and mounting the substrate including the solder balls and the first barrier wall to a carrier to form the substrate package. In some embodiments, the method further includes forming a non-conductive second barrier wall and a third barrier wall perpendicular to the first barrier wall and at two opp