CN-122028751-A - Bridging chip and chip packaging structure with same

CN122028751ACN 122028751 ACN122028751 ACN 122028751ACN-122028751-A

Abstract

The application discloses a bridging chip and a chip packaging structure with the bridging chip, the bridging chip comprises a substrate, a metal wiring layer formed on the substrate, a micro bump group formed on the substrate, wherein the metal wiring layer comprises a plurality of interconnection wires, the micro bump group comprises a first micro bump array and a second micro bump array, the first micro bump array and the second micro bump array are respectively used for being interconnected with two adjacent bare chips, the first micro bump array comprises a plurality of first micro bumps which are arranged in a set array mode, the second micro bump array comprises a plurality of second micro bumps which are arranged in a set array mode, the set array mode is a rectangular array or a staggered array, the first micro bumps, the second micro bumps and the interconnection wires are identical in number and correspond to each other one by one, and the length and the size of each corresponding first micro bump and each second micro bump are electrically connected through one interconnection wire and are consistent. The application can realize high-density and short-distance interconnection between the first micro-convex point and the second micro-convex point.

Inventors

ZHAO XUDONG
QIAO HAILONG
HE QIBIN

Assignees

北京华封集芯电子有限公司

Dates

Publication Date: 20260512
Application Date: 20251229

Claims (9)

1. A bridge chip for interconnecting two adjacent die in a chip package structure, comprising: A substrate; a metal wiring layer formed on the substrate, the metal wiring layer including a plurality of interconnect wires; The micro-bump group comprises a first micro-bump array and a second micro-bump array, wherein the first micro-bump array and the second micro-bump array are respectively used for bonding and interconnection with two adjacent bare chips in a one-to-one correspondence manner; the first micro-bump array comprises a plurality of first micro-bumps arranged in a set array form, the second micro-bump array comprises a plurality of second micro-bumps arranged in the set array form, and the set array form is a rectangular array or a staggered array; The first micro-bumps, the second micro-bumps and the interconnection wires are the same in number and in one-to-one correspondence, each corresponding first micro-bump is electrically connected with each corresponding second micro-bump through one interconnection wire, and the length sizes of the interconnection wires are consistent.
2. The bridge chip of claim 1, wherein the set array is a rectangular array, a first set pitch is provided between any two corresponding first micro bumps and second micro bumps in a lateral direction and a second set pitch is provided in a vertical direction, and the interconnection wire includes a first vertical section extending in the vertical direction and first bending sections extending from two ends of the first vertical section respectively and obliquely outwards.
3. The bridge chip of claim 2, wherein a third set pitch is provided between two adjacent micro bumps arranged in a lateral direction in the rectangular array, and a fourth set pitch is provided between two adjacent micro bumps arranged in a vertical direction, and the first set pitch is equal to the third set pitch.
4. The bridge chip of claim 1, wherein the set array is in the form of a staggered array, the staggered array includes a plurality of micro-bump columns arranged along a transverse direction, two adjacent micro-bump columns are offset from each other along a vertical direction, and a first set interval is arranged between any two mutually corresponding first micro-bumps and second micro-bumps along the transverse direction and a second set interval is arranged between any two mutually corresponding first micro-bumps and second micro-bumps along the vertical direction.
5. The bridge chip of claim 4, wherein each of the micro-bump columns comprises a plurality of micro-bumps arranged vertically, the interconnect wire comprises a second vertical section extending vertically and second bent sections extending obliquely outward from both ends of the second vertical section, respectively; Or each micro-convex point column comprises a plurality of micro-convex points which are distributed along the inclined direction relative to the vertical direction, and the whole interconnection wire extends along the vertical direction.
6. The bridge chip of claim 5, wherein each of the micro-bump columns includes a plurality of micro-bumps arranged vertically, and two adjacent micro-bump columns have a third set interval in a lateral direction, and the first set interval is equal to the third set interval.
7. The bridge chip of claim 6, wherein two adjacent micro-bump columns are vertically offset from each other by a fourth set interval, wherein two adjacent micro-bumps in each micro-bump column have a fifth set interval between them in the vertical direction, the fourth set interval is half of the fifth set interval, and the third set interval L is a fourth set interval t Multiple times.
8. A chip package structure, comprising a first die, a second die and the bridge chip of any one of claims 1 to 7, wherein the first die is provided with a third micro bump array on a region mated with the bridge chip, and the second die is provided with a fourth micro bump array on a region mated with the bridge chip; The third micro-bump array comprises a plurality of third micro-bumps which are arranged in the set array mode, and the number of the third micro-bumps is the same as that of the first micro-bumps and are in flip-chip bonding in a one-to-one correspondence manner; the fourth micro-bump array comprises a plurality of fourth micro-bumps which are arranged in the set array mode, and the fourth micro-bumps and the second micro-bumps are the same in number and are in flip-chip bonding in one-to-one correspondence.
9. The chip package structure of claim 8, wherein the first die is made based on a first process that is functionally matched to the first die, and the second die is made based on a second process that is functionally matched to the second die, the first process being different from the second process; Or, the first die and the second die are manufactured by adopting the same manufacturing process.

Description

Bridging chip and chip packaging structure with same Technical Field The application relates to the technical field of semiconductor packaging, in particular to a bridging chip and a chip packaging structure with the bridging chip. Background With the continuous development of semiconductor technology, multi-chip packages (MCPs) and system in package (sips) have received attention because of their ability to integrate multiple functional chips, improve system performance, and miniaturize. In these packaging structures, multiple dies (e.g., processors, memories, etc.) need to be efficiently and reliably interconnected to enable data transfer and signal exchange. Conventional interconnection methods typically employ wire bonding or wiring interconnection through the package substrate. However, the existing wiring interconnection scheme has the problems of low wiring density, long wiring distance and increased layer number, the low wiring density can limit the data transmission bandwidth between adjacent bare chips, and larger wiring space is required, so that the miniaturization of a packaging structure is not facilitated, and the long wiring distance and the increased layer number can lead to signal delay and crosstalk, and further increase power consumption and cost. Disclosure of Invention The present application aims to solve one of the technical problems in the related art to a certain extent. Therefore, the application provides a bridging chip and a chip packaging structure with the bridging chip. In order to achieve the above purpose, the application adopts the following technical scheme that a bridging chip is used for interconnecting two adjacent bare chips in a chip packaging structure and comprises the following steps: A substrate; a metal wiring layer formed on the substrate, the metal wiring layer including a plurality of interconnect wires; The micro-bump group comprises a first micro-bump array and a second micro-bump array, wherein the first micro-bump array and the second micro-bump array are respectively used for bonding and interconnection with two adjacent bare chips in a one-to-one correspondence manner; the first micro-bump array comprises a plurality of first micro-bumps arranged in a set array form, the second micro-bump array comprises a plurality of second micro-bumps arranged in the set array form, and the set array form is a rectangular array or a staggered array; The first micro-bumps, the second micro-bumps and the interconnection wires are the same in number and in one-to-one correspondence, each corresponding first micro-bump is electrically connected with each corresponding second micro-bump through one interconnection wire, and the length sizes of the interconnection wires are consistent. The application has the advantages that the first micro-bump array and the second micro-bump array which are used for respectively bonding and interconnecting with two adjacent bare chips are arranged, the corresponding first micro-bumps and the corresponding second micro-bumps are directly connected point to point through the interconnection wires, and the distribution of the micro-bumps in the first micro-bump array and the second micro-bump array is designed to be in rectangular array or staggered array arrangement. Therefore, high-density and short-distance interconnection between the first micro-convex points and the second micro-convex points can be realized, the space utilization rate can be improved, the signal transmission efficiency and reliability can be obviously improved, the signal delay is reduced, and the power consumption is reduced. Optionally, the set array is a rectangular array, a first set interval is provided between any two corresponding first micro-bumps and the second micro-bumps along a transverse direction, and a second set interval is provided along a vertical direction, and the interconnection wire comprises a first vertical section extending along the vertical direction and a first bending section extending from two ends of the first vertical section in an outward inclined manner. Optionally, a third set interval is arranged between two adjacent micro-bumps arranged along the transverse direction in the rectangular array, a fourth set interval is arranged between two adjacent micro-bumps arranged along the vertical direction, and the first set interval is equal to the third set interval. Optionally, the set array is in a staggered array form, the staggered array includes a plurality of micro-convex point columns arranged along a transverse direction, two adjacent micro-convex point columns are offset from each other along a vertical direction, and a first set interval is arranged between any two first micro-convex points and second micro-convex points which correspond to each other along the transverse direction and a second set interval is arranged between any two first micro-convex points and second micro-convex points along the vertical direction. Optionally