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CN-122028753-A - Semiconductor packaging structure and preparation method thereof

CN122028753ACN 122028753 ACN122028753 ACN 122028753ACN-122028753-A

Abstract

The application provides a semiconductor packaging structure and a preparation method thereof, wherein the semiconductor packaging structure comprises a first rigid insulating substrate, a second rigid insulating substrate and a first conductive structure, wherein the first conductive structure is arranged in a penetrating way along the thickness direction; the first rigid insulating substrate is arranged on one side of the first rigid insulating substrate, the built-in chip is electrically connected with the first conductive structure, the second rigid insulating substrate is arranged on one side of the built-in chip far away from the first rigid insulating substrate, the second rigid insulating substrate comprises a second conductive structure penetrating through the built-in chip in the thickness direction, and the built-in chip is electrically connected with the second conductive structure. According to the application, the thermal stress is balanced by the rigid substrates positioned on the two sides of the built-in chip, so that the warp deformation of the large-size intermediate layer in the thermal process is reduced, and the problem of warp exceeding standard caused by insufficient rigidity of the organic substrate and the problem of warp residual caused by mismatching of the single-layer glass substrate and the organic rewiring layer material are solved.

Inventors

  • ZHOU YANXU

Assignees

  • 苏州国显创新科技有限公司

Dates

Publication Date
20260512
Application Date
20260415

Claims (10)

  1. 1. A semiconductor package structure, comprising: The first rigid insulating substrate comprises a first conductive structure penetrating in the thickness direction; the built-in chip is arranged on one side of the first rigid insulating substrate and is electrically connected with the first conductive structure; the second rigid insulating substrate is arranged on one side, far away from the first rigid insulating substrate, of the built-in chip, the second rigid insulating substrate comprises a second conductive structure penetrating through the built-in chip along the thickness direction, and the built-in chip is electrically connected with the second conductive structure.
  2. 2. The semiconductor package according to claim 1, wherein the material of at least one of the first rigid insulating substrate and the second rigid insulating substrate comprises glass.
  3. 3. The semiconductor package according to claim 1, wherein the second rigid insulating substrate comprises a fiberglass cloth layer.
  4. 4. The semiconductor package according to claim 1, further comprising: an insulating filling layer which is arranged between the first rigid insulating substrate and the second rigid insulating substrate and at least coats the side wall of the built-in chip; the third conductive structure is arranged in the insulating filling layer, and the first conductive structure is electrically connected with the second conductive structure through the third conductive structure.
  5. 5. The semiconductor package according to claim 4, further comprising: the functional chip is arranged on one side of the second rigid insulating substrate far away from the built-in chip and is electrically connected with the built-in chip through the second conductive structure; the built-in chips comprise silicon bridge chips, the number of the functional chips is at least two, and at least two functional chips are electrically connected through the silicon bridge chips.
  6. 6. The semiconductor package according to claim 5, further comprising: The first rewiring layer is arranged on one side, close to the built-in chip, of the first rigid insulating substrate and comprises a first dielectric layer and a first circuit layer which are alternately stacked, wherein one side of the first circuit layer is electrically connected with the first conductive structure, and the other side of the first circuit layer is electrically connected with the built-in chip and/or the third conductive structure; The second redistribution layer is arranged on one side of the built-in chip, which is close to the second rigid insulating substrate, and comprises second dielectric layers and second circuit layers which are alternately stacked, wherein one side of the second circuit layer is electrically connected with the second conductive structure, and the other side of the second circuit layer is electrically connected with the built-in chip and/or the third conductive structure.
  7. 7. The semiconductor package according to claim 6, further comprising: a first conductor disposed between the second redistribution layer and the functional chip to electrically connect the second redistribution layer and the functional chip; The second conductor is arranged on one side of the first rigid insulating substrate, which is far away from the functional chip; The insulating packaging layer is arranged on one side, far away from the built-in chip, of the second redistribution layer and surrounds the functional chip.
  8. 8. The semiconductor package according to claim 1, further comprising: The circuit board is arranged on one side, far away from the built-in chip, of the first rigid insulating substrate, and the built-in chip is electrically connected with the circuit board through the first conductive structure.
  9. 9. A method of fabricating a semiconductor package, the method comprising: Providing a first rigid insulating substrate, wherein the first rigid insulating substrate comprises a first conductive structure penetrating in the thickness direction; a built-in chip is arranged on one side of the first rigid insulating substrate; And a second rigid insulating substrate is arranged on one side of the built-in chip far away from the first rigid insulating substrate, and the second rigid insulating substrate comprises a second conductive structure penetrating along the thickness direction.
  10. 10. The method of manufacturing a semiconductor package according to claim 9, wherein the disposing a built-in chip on one side of the first rigid insulating substrate comprises: forming a first rewiring layer on one side of the first rigid insulating substrate, wherein the first rewiring layer is electrically connected with the first conductive structure; Bonding the built-in chip with the first rewiring layer to electrically connect the built-in chip with the first rewiring layer; forming a plurality of third conductive structures arranged at intervals around the built-in chip; filling insulating filling materials around the built-in chip and the third conductive structure to form an insulating filling layer; before the side of the built-in chip away from the first rigid insulating substrate is provided with the second rigid insulating substrate, the method further comprises: forming a second redistribution layer on a side of the built-in chip and the insulating filling layer away from the first rigid insulating substrate, the second redistribution layer being electrically connected with the built-in chip and/or with the third conductive structure; the second rigid insulating substrate is arranged on one side, far away from the built-in chip, of the second redistribution layer, and the second conductive structure is electrically connected with the second redistribution layer.

Description

Semiconductor packaging structure and preparation method thereof Technical Field The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method thereof. Background With the technical development of the fields of artificial intelligence, high-performance computing and the like, the requirements on chip performance and integration level are continuously improved. Along with the gradual approach of the chip manufacturing process to the physical limit, the development speed tends to be slow, and the packaging structure and the preparation method thereof become important directions for improving the integration level and the performance of the chip. At present, one way to improve the integration density is to provide an interposer between the chip and the substrate. Disclosure of Invention In view of the above, the present application is directed to a semiconductor package structure and a method for manufacturing the same, so as to reduce the risk of warpage of a substrate. In view of the above object, the present application provides, in a first aspect, a semiconductor package structure including: The first rigid insulating substrate comprises a first conductive structure penetrating in the thickness direction; The built-in chip is arranged on one side of the first rigid insulating substrate and is electrically connected with the first conductive structure; the second rigid insulating substrate is arranged on one side of the built-in chip far away from the first rigid insulating substrate, and comprises a second conductive structure penetrating through the built-in chip along the thickness direction, and the built-in chip is electrically connected with the second conductive structure. Optionally, the material of at least one of the first rigid insulating substrate and the second rigid insulating substrate comprises glass. Optionally, the second rigid insulating substrate comprises a fiberglass cloth layer. Optionally, the method further comprises: the functional chip is arranged on one side of the second rigid insulating substrate far away from the built-in chip and is electrically connected with the built-in chip through the second conductive structure; the built-in chips comprise silicon bridge chips, the number of the functional chips is at least two, and at least two functional chips are electrically connected through the silicon bridge chips. Optionally, the method further comprises: an insulating filling layer which is arranged between the first rigid insulating substrate and the second rigid insulating substrate and at least coats the side wall of the built-in chip; the third conductive structure is arranged in the insulating filling layer, and the first conductive structure is electrically connected with the second conductive structure through the third conductive structure. Optionally, the method further comprises: The first rewiring layer is arranged on one side, close to the built-in chip, of the first rigid insulating substrate and comprises a first dielectric layer and a first circuit layer which are alternately stacked, wherein one side of the first circuit layer is electrically connected with the first conductive structure, and the other side of the first circuit layer is electrically connected with the built-in chip and/or the third conductive structure; The second redistribution layer is arranged on one side of the built-in chip, which is close to the second rigid insulating substrate, and comprises second dielectric layers and second circuit layers which are alternately stacked, wherein one side of the second circuit layer is electrically connected with the second conductive structure, and the other side of the second circuit layer is electrically connected with the built-in chip and/or the third conductive structure. Optionally, the method further comprises: a first conductor disposed between the second redistribution layer and the functional chip to electrically connect the second redistribution layer and the functional chip; The second conductor is arranged on one side of the first rigid insulating substrate, which is far away from the functional chip; The insulating packaging layer is arranged on one side, far away from the built-in chip, of the second redistribution layer and surrounds the functional chip. Optionally, the method further comprises: The circuit board is arranged on one side, far away from the built-in chip, of the first rigid insulating substrate, and the built-in chip is electrically connected with the circuit board through the first conductive structure. In a second aspect, the present application further provides a method for manufacturing a semiconductor package structure, including: Providing a first rigid insulating substrate, wherein the first rigid insulating substrate comprises a first conductive structure penetrating along the thickness direction; a built-in chip is arranged