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CN-122028763-A - Packaging structure and testing method

CN122028763ACN 122028763 ACN122028763 ACN 122028763ACN-122028763-A

Abstract

The invention relates to the technical field of semiconductors and discloses a packaging structure and a testing method. The packaging structure comprises a first through hole, a second through hole, a first lead unit and a second lead unit, wherein the first through hole is arranged on a cathode molybdenum sheet and is overlapped with a partial area of a gate electrode of a target cell, the second through hole is arranged on a cathode tube shell, the first through hole and the second through hole Kong Chuantong are formed in the first through hole, the first lead unit comprises a first lead end which is in contact with the gate electrode of the target cell and a first lead, the first end is connected with the first lead end, the second end is led out through the first through hole and the second through hole, and the second lead unit comprises a second lead end which is in contact with the cathode molybdenum sheet and a second lead, and the first end is connected with the second lead end and the second end is led out through the second through hole. The invention can directly measure the converter parameters of the cell level in the turn-off process of the power device.

Inventors

  • LIU HUI
  • ZENG RONG
  • WEI XIAOGUANG
  • WU JINPENG
  • ZHANG HAO
  • JIAO QIANQIAN
  • ZHAO XIANGYU
  • LI XIAOZHAO
  • WANG YAOHUA

Assignees

  • 北京怀柔实验室
  • 清华大学

Dates

Publication Date
20260512
Application Date
20260410

Claims (14)

  1. 1. A package structure including a power device including a power chip, a cathode molybdenum sheet, and a cathode casing, and a gate driving unit for applying a reverse voltage between a gate ring and a cathode of the power chip during a turn-off test, the package structure comprising: The first through hole is arranged on the cathode molybdenum sheet and at least overlaps with a partial region of the gate electrode of the first target cell of the power chip; The second through hole is arranged on the cathode tube shell, and the second through hole and the first through hole are mutually communicated; The first lead unit comprises a first lead end, a first lead and a second lead, wherein the first lead end is in contact with the gate electrode of the first target cell, the first end of the first lead is connected with the first lead end, and the second end of the first lead is led out from the second through hole through the first through hole; The second lead unit comprises a second lead end and a second lead, wherein the second lead end is in contact with the cathode molybdenum sheet, the first end of the second lead is connected with the second lead end, and the second end of the second lead is led out through the second through hole.
  2. 2. The package structure according to claim 1, the packaging structure is characterized by further comprising: a first lead groove connected with the second through hole, The second end of the first lead is led out from the first lead groove through the first through hole, the second through hole and the first lead groove, and the second end of the second lead is led out from the first lead groove through the second through hole.
  3. 3. The package structure according to claim 2, the packaging structure is characterized by further comprising: The third through hole is arranged on the cathode molybdenum sheet and at least overlaps with a partial region of a gate electrode of a second target cell of the power chip, and the distance between the first target cell and the gate electrode ring is different from the distance between the second target cell and the gate electrode ring; a fourth through hole arranged on the cathode tube shell, wherein the fourth through hole and the third through hole are mutually communicated in series; The third lead unit comprises a third lead end and a third lead, wherein the third lead end is in contact with the gate electrode of the second target cell, the first end of the third lead is connected with the third lead end, and the second end of the third lead is led out from the fourth through hole through the third through hole; And the fourth lead unit comprises a fourth lead end, a fourth lead and a fourth lead, wherein the fourth lead end is in contact with the cathode molybdenum sheet, the first end of the fourth lead is connected with the fourth lead end, and the second end of the fourth lead is led out through the fourth through hole.
  4. 4. The package structure according to claim 3, the packaging structure is characterized by further comprising: a second lead groove connected with the fourth through hole, The second end of the third lead is led out from the second lead groove through the third through hole, the fourth through hole and the fourth lead, and the second end of the fourth lead is led out from the second lead groove through the fourth through hole.
  5. 5. The package structure of claim 4, wherein the gate in the first target cell and the gate in the second target cell are located in a same radial direction of the power chip, and the first lead groove and the second lead groove are a same groove.
  6. 6. The package structure of claim 5, wherein the cathode of one of the first and second target cells is located on a ring of cathode rings furthest from the gate ring and the cathode of the other cell is located on a ring of cathode rings closest to the gate ring.
  7. 7. The package structure of claim 3, wherein a radius of the first via is less than or equal to a radius of the second via, and a radius of the third via is less than or equal to a radius of the fourth via.
  8. 8. The package structure of claim 7, wherein the first through hole and the third through hole have a radius of 1-4mm, and the second through hole and the fourth through hole have a radius of 2-6mm.
  9. 9. The package structure of claim 7, wherein the first via is aligned with a center of the second via and the third via is aligned with a center of the fourth via.
  10. 10. The package structure of claim 3, wherein the first, second, third and fourth lead terminals are fine probes or spring probes.
  11. 11. The package structure of claim 3, wherein the first, second, third and fourth leads are twisted pair shielding wires.
  12. 12. The package structure of claim 1, wherein the power device is an IGCT device or an IGTO device.
  13. 13. A test method applied to the package structure according to any one of claims 1 to 12, the package structure further comprising a third via overlapping at least a partial region of a gate electrode of a second target cell of the power chip, a third lead unit including a third lead terminal and a third lead, and a fourth lead unit including a fourth lead terminal and a fourth lead, the test method comprising: And detecting the voltage between the first lead and the second lead by adopting voltage detection equipment to obtain the voltage of the PN junction between the gate electrode and the cathode electrode of the first target cell.
  14. 14. The method of testing of claim 13, further comprising: detecting the voltage between the third lead and the fourth lead by adopting voltage detection equipment to obtain the voltage of a PN junction between the gate electrode and the cathode electrode of the second target cell; and calculating the difference value of the voltage of the PN junction between the gate electrode and the cathode of the first target cell and the voltage of the PN junction between the gate electrode and the cathode of the second target cell to obtain a voltage difference.

Description

Packaging structure and testing method Technical Field The invention relates to the technical field of semiconductors, in particular to a packaging structure and a testing method. Background IGCT (INTERGRATED GATE Commutated Thyristor, integrated gate commutated thyristor) refers to a new power semiconductor device integrating a packaged GCT chip with a gate drive unit. The IGCT has the advantages of low loss, high switching frequency, high commutation speed, low heat dissipation, high reliability and the like, and has important value in high-voltage and high-current application scenes. IGCT devices can be classified into asymmetric, reverse-conducting, reverse-resistive, wavy base, etc. according to structural classification. Taking an asymmetric IGCT device as an example, a typical structure of a GCT cell is shown in fig. 1, and the GCT cell has a PNPN four-layer three-junction structure in a longitudinal direction, and specifically includes a cathode, a gate ring (not shown), an n+ emitter, a p base region, an n base region, an n+ buffer layer, a p+ emitter and an anode. In the transverse structure, the GCT chip is provided with strip-shaped unit cells which are concentrically and annularly arranged, the gates of the unit cells are distributed around the strip-shaped cathode, and the metal areas of the gates at different positions are connected and commonly led out from the gate ring (as shown in figure 3 a). The turn-on and turn-off principles of the IGCT device are shown in fig. 2a and 2b, respectively, in which a PN junction (J3 junction) between the gate and the cathode of the IGCT device is quickly restored to be blocked by applying a negative pulse voltage (or current) of high magnitude and high rate of rise between the gate and the cathode during turn-off, resulting in transfer of an anode current from the cathode to the gate, thereby completing the commutation process. At this time, since positive feedback between the NPN transistor on the cathode side and the PNP transistor on the anode side is broken, turning off is gradually achieved. During turn-off of IGCT devices, cells farther from the gate ring (i.e., cells of the far gate ring) have a longer path for the current to flow and thus have a greater impedance and inductance due to their larger lateral dimensions, and therefore the cathode current of these cells requires a longer time to switch to the gate ring, resulting in slower turn-off speeds than cells closer to the gate ring (i.e., cells of the near gate ring) can complete the current switching and form a depletion layer faster. The difference in turn-off speed of the cells at different positions causes the problem that the cells close to the gate ring may enter the turn-off state in advance, while the cells far away from the gate ring are still turned on due to incomplete charge extraction, so that local current concentration is formed, the local area of the chip may be overheated and the electric field intensity is too high, and finally the chip is damaged or the reliability is reduced. The above phenomenon is also called a back-delay effect, and has serious negative influence on the service life of the IGCT device in a practical application scenario. In order to analyze and solve the damage caused by the post-delay effect, the process of the far gate ring cell and the near gate ring cell replacement process needs to be measured so as to compare and analyze the difference of the turn-off partial pressures of the far/near gate ring cells, thereby guiding the optimization of the chip cell layout and the improvement of the driving circuit design. However, in the existing shutdown test method, the GCT chip needs to be integrally crimped to the tube shell or packaged before the GCT chip can be connected with an external circuit for performing a test, and the voltage V J3 of the junction J3 inside the IGCT device is further deduced by collecting the voltage difference between the gate ring and the cathode (i.e. the voltage V GK of the tube shell and the gate-cathode interface of the driving board) on the test circuit shown in fig. 4. Because the gate metal areas at different positions are connected and jointly led out by the gate ring, the V J3 obtained by testing is the total voltage and current characteristic of all cells of the GCT under the parallel connection, and the current conversion process and the electrical parameters of a certain cell in the IGCT device cannot be obtained independently, so that the current conversion difference of the cells of the far/near gate ring cannot be analyzed. Disclosure of Invention The invention aims to provide a packaging structure and a testing method, which reduce the influence of the spurious parameters of a tube shell on a testing result on the premise of not changing a current path in the current conversion process, so that the cell-level current conversion parameters can be directly measured in the turn-off process of a power device, the measuri