CN-122028767-A - Bump packaging structure and bump packaging method

Abstract

The application provides a bump packaging structure and a bump packaging method, and relates to the technical field of semiconductor packaging. The bump packaging structure comprises a chip with a bonding pad, a buffer layer and a wiring layer, wherein a plurality of first conductive columns are arranged on the bonding pad at intervals, and the first conductive columns are electrically connected with the bonding pad. The buffer layer is used for coating the plurality of first conductive posts, the wiring layer is connected with the buffer layer, and the wiring layer is electrically connected with at least one of the first conductive posts and the bonding pads. The buffer layer can absorb stress of the wiring layer, prevent structural delamination and breakage, and improve conductivity and structural reliability.

Inventors

• JIAN ZHIHONG
• XU YUPENG
• ZHONG LEI
• HE ZHENGHONG

Assignees

• 甬矽半导体(宁波)有限公司

Dates

Publication Date

20260512

Application Date

20260413

Claims (20)

1. 1. A bump package structure, comprising: A chip with a bonding pad, wherein a plurality of first conductive columns are arranged on the bonding pad at intervals, and the first conductive columns are electrically connected with the bonding pad; a buffer layer, wherein the buffer layer coats a plurality of the first conductive columns; and a wiring layer electrically connected to at least one of the first conductive post and the pad, the wiring layer being connected to the buffer layer.
2. 2. The bump package of claim 1, wherein the buffer layer is disposed between a plurality of the first conductive pillars, the buffer layer and the plurality of first conductive pillars together form a buffer body, the buffer body is provided with an arcuate surface that is concave inward or convex outward, and the wiring layer is in contact with the arcuate surface.
3. 3. The bump package structure of claim 2, wherein the buffer body is provided with a first groove, and the wiring layer is in contact with a groove wall of the first groove and is electrically connected to the plurality of first conductive pillars, respectively.
4. 4. The bump package of claim 3, wherein the first recess exposes a surface of the first conductive post, and a height of the first conductive post near the center of the pad is lower than a height of the first conductive post away from the center of the pad among the plurality of first conductive posts.
5. 5. The bump package of claim 3, wherein the bottom of the first recess is arcuate.
6. 6. The bump package structure of claim 2, further comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is provided with a first opening exposing the bonding pad, the buffer body is disposed in the first opening, the second dielectric layer covers the first dielectric layer and fills the first opening, a second opening is formed in the second dielectric layer to expose the buffer body, and the wiring layer is disposed in the second opening.
7. 7. The bump package of claim 1, wherein the buffer layer comprises a plurality of buffer posts, each of the first conductive posts is covered by one of the buffer posts, the plurality of buffer posts are spaced apart to form a first gap, the wiring layer fills the first gap, and the wiring layer is electrically connected to the pad.
8. 8. The bump package of claim 7 wherein the buffer post has a second recess on a side thereof remote from the pad.
9. 9. The bump package of claim 8, wherein the wiring layer is disposed along a wall of the second groove at the second groove, and forms a third groove.
10. 10. The bump package structure of claim 7, further comprising a sidewall buffer post, wherein the sidewall buffer post is located at an outer periphery of the buffer post, the sidewall buffer post is connected to the pad, a fourth groove is formed on a side of the sidewall buffer post facing the buffer post, and the wiring layer fills the fourth groove.
11. 11. The bump package structure of claim 10, further comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is provided with a first opening exposing the bonding pad, a plurality of the buffer pillars and the sidewall buffer pillars are all disposed in the first opening, the second dielectric layer covers the first dielectric layer and fills the first opening, a second opening is formed in the second dielectric layer to expose the bonding pad, the buffer pillars and the sidewall buffer pillars, and the wiring layer is disposed in the second opening.
12. 12. The bump package of claim 11 wherein the wiring layer is further filled between the sidewall buffer post and the second dielectric layer.
13. 13. The bump package of claim 1 wherein the routing layer is recessed at the bond pad.
14. 14. The bump package of any one of claims 1 to 13 further comprising a third dielectric layer covering the wiring layer, the third dielectric layer having a third opening exposing the wiring layer; the third opening is sequentially provided with a second conductive column and a bump which are connected, and the second conductive column is electrically connected with the wiring layer.
15. 15. A bump packaging method, comprising: forming a plurality of spaced first pillars on pads of a chip; Forming a buffer layer coating a plurality of first columns; And if the first column body is made of metal, the wiring layer is electrically connected with at least one of the first column body and the bonding pad.
16. 16. The bump packaging method according to claim 15, wherein the step of forming a buffer layer covering a plurality of the first pillars comprises: Forming a first dielectric layer with a first opening on the surface of the chip, wherein the first opening exposes the bonding pad; Forming a photosensitive layer having a third opening in the first opening, the third opening having a smaller cross-section than the first opening, the third opening exposing the pad and the first pillar; and forming a buffer layer coating a plurality of first pillars in the third opening.
17. 17. The bump packaging method according to claim 16, wherein after the step of forming a buffer layer covering a plurality of the first pillars, comprising: Removing a part of the photosensitive layer in the first opening, and forming a second gap between the rest photosensitive layer and the first dielectric layer; Forming a second dielectric layer filling the second gap and covering the first dielectric layer, wherein the second dielectric layer is provided with a second opening exposing the buffer layer; Removing the residual photosensitive layer in the first opening, and forming a third gap between the buffer layer and the second dielectric layer; In the step of forming a wiring layer connected to the buffer layer, the wiring layer fills the third gap.
18. 18. The bump packaging method according to claim 16, wherein after the step of forming a buffer layer covering a plurality of the first pillars, comprising: The buffer layer and the plurality of first conductive columns form a buffer main body together, and a first groove is formed in the buffer main body; in the step of forming the wiring layer connected to the buffer layer, the wiring layer is laid along the first groove.
19. 19. The bump packaging method according to claim 16, wherein after the step of forming a buffer layer covering a plurality of the first pillars, comprising: forming a plurality of spaced buffer posts and side wall buffer posts on the buffer layer at the periphery of the plurality of buffer posts, each buffer post wrapping one of the first posts; in the step of forming a wiring layer connected to the buffer layer, the wiring layer fills the first gap.
20. 20. The bump packaging method according to claim 19, wherein after the step of forming a plurality of spaced buffer posts and sidewall buffer posts located at the periphery of the plurality of buffer posts on the buffer layer, comprising: forming a second groove on the buffer post; And/or forming a fourth groove on the side wall buffer post; In the step of forming the wiring layer connected with the buffer layer, the wiring layer fills the fourth groove, the wiring layer is arranged along the groove wall of the second groove, and a third groove is formed on the surface of the wiring layer.

Description

Bump packaging structure and bump packaging method Technical Field The present invention relates to the field of semiconductor packaging technology, and in particular, to a bump packaging structure and a bump packaging method. Background With the rapid development of the semiconductor industry, a photoresist layer is coated on the surface of a chip pad by using a coating process, a new wiring pattern is defined by using an exposure and development mode, and then a new metal circuit is manufactured by using an electroplating process to form a rewiring layer. Therefore, the positions (I/O ends) of the circuit joints of the chips in the original design can be changed through the wafer-level metal wiring process and the bump process, the number of the bumps is increased, and the bump spacing is reduced to improve the product performance. In the re-wiring process, due to inconsistent thermal expansion coefficients of dielectric layer materials, wiring layers, chip materials and the like, the wiring layers are easy to generate welding layering at the positions of the opening joints of the chip bonding pads, so that electrical failure is caused, or as the thickness and the line width of the wiring layers are reduced, the surface of the wiring layers is easy to generate skin effect, so that current only flows on the surface, but is not evenly distributed in the sectional area of the whole wiring layers, and the electrical function of the wiring layers is reduced. Disclosure of Invention The invention aims to provide a bump packaging structure and a bump packaging method, which can absorb thermal stress of materials, prevent welding layering and improve conductive performance and electrical connection reliability by forming a buffer layer at the position of a bonding pad opening contact point of a chip. In a first aspect, the present invention provides a bump package structure, including: A chip with a bonding pad, wherein a plurality of first conductive columns are arranged on the bonding pad at intervals, and the first conductive columns are electrically connected with the bonding pad; a buffer layer, wherein the buffer layer coats a plurality of the first conductive columns; and a wiring layer electrically connected to at least one of the first conductive post and the pad, the wiring layer being connected to the buffer layer. In an alternative embodiment, the buffer layer is disposed between a plurality of the first conductive pillars, the buffer layer and the plurality of first conductive pillars together form a buffer body, the buffer body is provided with an inward concave or outward convex arc surface, and the wiring layer is in contact with the arc surface. In an alternative embodiment, the buffer body is provided with a first groove, and the wiring layer is in contact with the walls of the first groove and is electrically connected with the plurality of first conductive posts, respectively. In an alternative embodiment, the first grooves expose a surface of the first conductive pillars, and a height of the first conductive pillars near the center of the pad is lower than a height of the first conductive pillars away from the center of the pad among the plurality of first conductive pillars. In an alternative embodiment, the bottom of the first groove is arc-shaped. In an optional embodiment, the semiconductor package further includes a first dielectric layer and a second dielectric layer, the first dielectric layer is provided with a first opening exposing the bonding pad, the buffer body is disposed in the first opening, the second dielectric layer covers the first dielectric layer and fills the first opening, a second opening is formed in the second dielectric layer to expose the buffer body, and the wiring layer is disposed in the second opening. In an alternative embodiment, the buffer layer comprises a plurality of buffer posts, each of the first conductive posts is covered by one of the buffer posts, the plurality of buffer posts are arranged at intervals to form a first gap, the first gap is filled by the wiring layer, and the wiring layer is electrically connected with the bonding pad. In an alternative embodiment, a second groove is provided on a side of the buffer post remote from the bonding pad. In an alternative embodiment, the wiring layer is disposed along a wall of the second groove at the second groove, and forms a third groove. In an optional embodiment, the semiconductor package further comprises a side wall buffer column, the side wall buffer column is located at the periphery of the buffer column and connected to the bonding pad, a fourth groove is formed in one side, facing the buffer column, of the side wall buffer column, and the wiring layer fills the fourth groove. In an optional embodiment, the semiconductor package further includes a first dielectric layer and a second dielectric layer, the first dielectric layer is provided with a first opening exposing the bonding pad, a plural