CN-122028769-A - Passivation layer manufacturing process

CN122028769ACN 122028769 ACN122028769 ACN 122028769ACN-122028769-A

Abstract

The application discloses a passivation layer manufacturing process which comprises the steps of S1, providing a semiconductor device, sequentially covering a top layer oxide layer and a first passivation layer on the top of the semiconductor device, removing the top layer oxide layer and the first passivation layer of a preset area through photoetching and etching processes to enable the metal pad to be exposed, S3, depositing a second passivation layer, and S4, carrying out etching process on the second passivation layer, wherein the rest of the second passivation layer covers the vertical side wall exposed by the top layer oxide layer and the vertical side wall exposed by the first passivation layer, and the rest of the first passivation layer and the second passivation layer form the passivation layer of the semiconductor device. According to the scheme, the passivation layer can provide water vapor isolation performance.

Inventors

HU JIARUI
MI KUI
LI KUNLE

Assignees

华虹半导体制造(无锡)有限公司

Dates

Publication Date: 20260512
Application Date: 20260116

Claims (6)

1. A passivation layer fabrication process, comprising: The method comprises the steps of S1, providing a semiconductor device, wherein the top of the semiconductor device is sequentially covered with a top oxide layer and a first passivation layer, and the top oxide layer covers a metal pad at the top of the semiconductor device; s2, removing the top oxide layer and the first passivation layer in a preset area through photoetching and etching processes so that the metal bonding pad is exposed; s3, depositing a second passivation layer, wherein the second passivation layer covers the exposed surface of the metal pad, the top oxide layer and the first passivation layer; S4, carrying out an etching process on the second passivation layer, wherein the remaining second passivation layer covers the vertical side wall exposed by the top oxide layer and the vertical side wall exposed by the first passivation layer; wherein the remaining first passivation layer and second passivation layer constitute a passivation layer of the semiconductor device.
2. The passivation layer manufacturing process of claim 1, wherein the first passivation layer is a silicon nitride layer.
3. The passivation layer manufacturing process of claim 1, wherein the second passivation layer is a silicon nitride layer.
4. A passivation layer manufacturing process according to claim 3, characterized in that in S3 the second passivation layer is deposited by a plasma chemical vapor deposition process.
5. The passivation layer manufacturing process according to claim 1, wherein in S3, the thickness of the deposited second passivation layer is 300 a or more.
6. A passivation layer manufacturing process according to claim 3, characterized in that in S4 the second passivation layer is etched by a dry etching process.

Description

Passivation layer manufacturing process Technical Field The application relates to the technical field of semiconductor manufacturing, in particular to a passivation layer manufacturing process. Background In the storage, transportation and working processes of the semiconductor chip, the internal circuit is extremely easy to be corroded by external water vapor permeation, acid-base substance corrosion and oxidation reaction, so that the problems of failure of a metal interconnection layer, electric property drift and the like are caused. The passivation layer is used as a protection barrier of the top layer of the chip, is one of core structures for guaranteeing the long-term reliability and stability of the chip, and is indispensable in advanced packaging and integrated circuit manufacturing. For the passivation layer commonly used at present, after the passivation layer is etched to expose the metal bonding pad below, part of the top oxide layer covered on the metal bonding pad is exposed, so that the position is more easily invaded by water vapor, and the water vapor blocking capability of the passivation layer is affected. When the passivation layer of the chip has insufficient water vapor blocking capability, especially when an Ultra Low-k (ULK) material is used in the back-end-of-line (post-end-of-line) process of chip fabrication, the performance of the chip may be very susceptible, for example, the capacitance offset of MOM (Metal-Oxide-Metal) may be increased, which may affect the end-use of the chip. Disclosure of Invention The application provides a passivation layer manufacturing process which can solve the problem that the passivation layer has insufficient water vapor blocking capability in the related art. The embodiment of the application provides a passivation layer manufacturing process, which comprises the following steps: The method comprises the steps of S1, providing a semiconductor device, wherein the top of the semiconductor device is sequentially covered with a top oxide layer and a first passivation layer, and the top oxide layer covers a metal pad at the top of the semiconductor device; s2, removing the top oxide layer and the first passivation layer in a preset area through photoetching and etching processes so that the metal bonding pad is exposed; s3, depositing a second passivation layer, wherein the second passivation layer covers the exposed surface of the metal pad, the top oxide layer and the first passivation layer; S4, carrying out an etching process on the second passivation layer, wherein the remaining second passivation layer covers the vertical side wall exposed by the top oxide layer and the vertical side wall exposed by the first passivation layer; wherein the remaining first passivation layer and second passivation layer constitute a passivation layer of the semiconductor device. In some embodiments, the first passivation layer is a silicon nitride layer. In some embodiments, the second passivation layer is a silicon nitride layer. In some embodiments, in the S3, the second passivation layer is deposited by a plasma chemical vapor deposition process. In some embodiments, in S3, the deposited second passivation layer has a thickness of 300 angstroms or more. In some embodiments, in the S4, the second passivation layer is etched by a dry etching process. The technical scheme of the application at least comprises the following advantages: 1. Through on first passivation layer, regrowth one deck second passivation layer, and the second passivation layer can wrap up the top layer oxide layer that exposes because the metal pad opens the process, has avoided steam to invade from this top layer oxide layer department that exposes, has improved the steam isolation performance of the passivation layer that finally obtains, and then can reduce MOM electric capacity skew, guarantee chip performance stability. Drawings In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art. FIG. 1 is a flow chart of a passivation layer fabrication process provided by an exemplary embodiment of the present application; Fig. 2 to fig. 5 are schematic views of a device structure in the implementation process of a passivation layer manufacturing process according to an exemplary embodiment of the present application; Fig. 6 is a graph comparing the results of reliability tests of different MOM devices provided by an exemplary embodiment of the present application. Reference numerals illustrate: 1. The semiconductor device comprises a first barrier layer, a low-dielectric-constant dielectric layer