CN-122028770-A - Multi-chip packaging structure and manufacturing process thereof

Abstract

The invention relates to a multi-chip packaging structure and a manufacturing process thereof, in the manufacturing process of the multi-chip packaging structure, the space between any two adjacent first semiconductor chips is set to be a first distance, the space between any two adjacent second semiconductor chips is set to be a second distance, the second distance is larger than the first distance, the warping of the multi-chip packaging structure can be effectively restrained, further, a plurality of first reinforcing columns are formed in the edge area of a first redistribution circuit layer, and a plurality of second reinforcing columns are formed in the edge area of a second redistribution circuit layer, so that the projection of the second reinforcing columns on the first surface of a carrier substrate is not overlapped with the projection of the first reinforcing columns on the first surface of the carrier substrate, and the warping of the multi-chip packaging structure can be further restrained through the arrangement.

Inventors

• SONG JILONG
• Tian yanan
• LIU HUI

Assignees

• 日月新半导体(威海)有限公司

Dates

Publication Date

20260512

Application Date

20260413

Claims (9)

1. 1. A manufacturing process of a multi-chip packaging structure is characterized by comprising the following steps of: Providing a carrier substrate, forming a temporary bonding layer on the first surface of the carrier substrate, and forming a first redistribution circuit layer on the temporary bonding layer; Providing a plurality of first semiconductor chips, and mounting the plurality of first semiconductor chips to the first redistribution line layer at a first temperature such that a pitch between any adjacent two of the first semiconductor chips is a first distance; Forming a plurality of first reinforcing columns in the edge area of the first redistribution line layer, and forming a plurality of first conductive columns electrically connected with the first redistribution line layer on the first redistribution line layer, wherein the height of the first conductive columns is larger than that of the first reinforcing columns; forming a first plastic sealing layer on the first redistribution circuit layer; forming a second redistribution circuit layer on the first plastic sealing layer, so that a plurality of the first conductive posts are electrically connected with the second redistribution circuit layer; Providing a plurality of second semiconductor chips, and mounting the plurality of second semiconductor chips to the second redistribution line layer at a second temperature such that a spacing between any adjacent two of the second semiconductor chips is a second distance, the first temperature being greater than the second temperature, the second distance being greater than the first distance; Forming a plurality of second reinforcing columns in the edge area of the second redistribution line layer, so that the projection of the second reinforcing columns on the first surface of the carrier substrate is not overlapped with the projection of the first reinforcing columns on the first surface of the carrier substrate; Forming a second plastic sealing layer on the second redistribution circuit layer; and then removing the carrier substrate and forming a plurality of conductive terminals on the surface of the first redistribution line layer.
2. 2. The process for manufacturing a multi-chip package structure as recited in claim 1, wherein the first redistribution circuitry layer and the second redistribution circuitry layer each comprise a plurality of dielectric layers and And a metal conductive layer embedded in the multi-layer dielectric layer.
3. 3. The process for manufacturing a multi-chip package according to claim 1, wherein the first temperature is 200-300 ℃ and the second temperature is 100-150 ℃.
4. 4. The process for manufacturing a multi-chip package structure according to claim 1, wherein a ratio of the second distance to the first distance is 1.2-1.8.
5. 5. The process for manufacturing a multi-chip package according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are square chips or rectangular chips.
6. 6. The process of claim 5, wherein when the first semiconductor chip and the second semiconductor chip are square chips, the side length of the second semiconductor chip is longer than the side length of the first semiconductor chip, and when the first semiconductor chip and the second semiconductor chip are rectangular chips, the long side of the second semiconductor chip is longer than the long side of the first semiconductor chip.
7. 7. The process for manufacturing a multi-chip package according to claim 6, wherein a ratio of a side length of the second semiconductor chip to a side length of the first semiconductor chip is 1.5-2 or a ratio of a long side of the second semiconductor chip to a long side of the first semiconductor chip is 1.5-2.
8. 8. The process of claim 1, wherein the ratio of the height of the first reinforcement post to the thickness of the first molding layer is 0.6-0.8, and the ratio of the height of the second reinforcement post to the thickness of the second molding layer is 0.6-0.8.
9. 9. A multi-chip package structure is characterized in that the multi-chip package structure is prepared by adopting the manufacturing process according to any one of claims 1-8.

Description

Multi-chip packaging structure and manufacturing process thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a multi-chip packaging structure and a manufacturing process thereof. Background The semiconductor package is a key structure for connecting a chip with an external circuit and realizing function integration, and the semiconductor package organically combines components such as the chip, a lead frame, a packaging material and the like through a precise process to form a complete electronic module capable of independently working. The packaging body not only provides physical protection for the chip and prevents the chip from being mechanically damaged or corroded by environment in the transportation and use processes, but also realizes high-efficiency electrical connection between the chip and an external circuit through internal wiring, thereby ensuring stable transmission of signals. With the rapid development of semiconductor technology, the package has evolved from a simple protective housing to a complex system with multiple functions such as heat dissipation management, electromagnetic shielding, power distribution, and the like, and particularly, under the promotion of advanced packaging technologies such as Flip Chip (Flip Chip), wafer Level Packaging (WLP), 3D integration, and the like, the package plays an increasingly important role in improving the Chip performance, reducing the system volume, reducing the power consumption, and the like, and becomes one of the core supports for miniaturization and high performance of modern electronic equipment. How to solve the warpage problem of the semiconductor package has attracted a great deal of attention in the industry. Disclosure of Invention The invention aims to overcome the defects in the prior art and provides a multi-chip packaging structure and a manufacturing process thereof. In order to achieve the above object, the present invention adopts a technical scheme that a manufacturing process of a multi-chip package structure includes the following steps: Providing a carrier substrate, forming a temporary bonding layer on the first surface of the carrier substrate, and forming a first redistribution circuit layer on the temporary bonding layer. Providing a plurality of first semiconductor chips, and mounting the plurality of first semiconductor chips to the first redistribution line layer at a first temperature such that a pitch between any adjacent two of the first semiconductor chips is a first distance. And forming a plurality of first reinforcing columns in the edge area of the first redistribution line layer, and forming a plurality of first conductive columns which are electrically connected with the first redistribution line layer on the first redistribution line layer, wherein the height of the first conductive columns is larger than that of the first reinforcing columns. A first molding layer is then formed over the first redistribution layer. And forming a second redistribution circuit layer on the first plastic sealing layer, so that a plurality of the first conductive posts are electrically connected with the second redistribution circuit layer. Providing a plurality of second semiconductor chips, and mounting the plurality of second semiconductor chips to the second redistribution line layer at a second temperature, wherein the interval between any two adjacent second semiconductor chips is a second distance, the first temperature is greater than the second temperature, and the second distance is greater than the first distance. And forming a plurality of second reinforcing columns in the edge area of the second redistribution line layer, so that the projection of the second reinforcing columns on the first surface of the carrier substrate is not overlapped with the projection of the first reinforcing columns on the first surface of the carrier substrate. And forming a second plastic sealing layer on the second redistribution circuit layer. And then removing the carrier substrate and forming a plurality of conductive terminals on the surface of the first redistribution line layer. As a preferred embodiment, the first redistribution line layer and the second redistribution line layer each include a plurality of dielectric layers and a metal conductive layer embedded in the plurality of dielectric layers. As a preferred embodiment, the first temperature is in the range of 200-300 ℃ and the second temperature is in the range of 100-150 ℃. As a preferred embodiment, the ratio of the second distance to the first distance is 1.2-1.8. As a preferred embodiment, the first semiconductor chip and the second semiconductor chip are square chips or rectangular chips. As a preferred embodiment, when the first semiconductor chip and the second semiconductor chip are square chips, the side length of the second semiconductor chip is larger than the side length of the first semiconductor chip,