CN-122028773-A - Semiconductor package with edge side interconnect and semiconductor package assembly and method of forming the same

Abstract

The present disclosure discloses a semiconductor package with edge side interconnect and a semiconductor package assembly and method of forming the same. An Integrated Circuit (IC) stack includes a plurality of Integrated Circuit (IC) structures horizontally separated from each other, wherein each IC structure includes a top surface, a bottom surface opposite the top surface, and four sidewalls including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, wherein the area of the bottom surface or the top surface is greater than the area of either sidewall, a laterally extending RDL structure covering each first sidewall of the plurality of IC structures, and an upwardly extending thermally conductive layer between two adjacent IC structures.

Inventors

• TANG HEMING
• LU CHAOQUN

Assignees

• 铨心半导体异质整合股份有限公司
• 钰创科技股份有限公司

Dates

Publication Date

20260512

Application Date

20250908

Priority Date

20250221

Claims (20)

1. 1. An IC stack, comprising: A plurality of Integrated Circuit (IC) structures horizontally separated from each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four side walls, wherein the four side walls are provided with a first side wall, a second side wall, a third side wall and a fourth side wall; A laterally extending RDL structure covering each of the first sidewalls of the plurality of IC structures, an An upwardly extending thermally conductive layer between two adjacent IC structures.
2. 2. The IC stack of claim 1, further comprising a laterally extending thermally conductive layer covering each second sidewall of the plurality of IC structures and thermally coupled to the upwardly extending thermally conductive layer, wherein the laterally extending RDL structure is opposite the laterally extending thermally conductive layer and the upwardly extending thermally conductive layer and/or the laterally extending thermally conductive layer has a thermal conductivity higher than that of silicon.
3. 3. The IC stack of claim 2, wherein the upwardly extending thermally conductive layer or the laterally extending thermally conductive layer comprises BN, alN, W, siC or copper.
4. 4. The IC stack of claim 1, further comprising an upwardly extending RDL structure overlying each third sidewall of the plurality of IC structures, wherein the upwardly extending RDL structure is electrically connected to the laterally extending RDL structure.
5. 5. The IC stack of claim 4, wherein each IC structure comprises a DRAM semiconductor die, and the IC stack is an HBM-compatible structure.
6. 6. The IC stack of claim 4, further comprising a logic control chip located below and electrically connected to the laterally extending RDL structure of the IC stack.
7. 7. The IC stack of claim 6, wherein each of the IC structures comprises a DRAM semiconductor die comprising a plurality of memory I/O pads, the logic control die comprises a plurality of logic I/O pads, and the plurality of memory I/O pads of each DRAM semiconductor die are electrically coupled to the plurality of logic I/O pads through the laterally extending RDL structure.
8. 8. The IC stack of claim 7, wherein the memory I/O pads do not include electrostatic discharge (ESD) protection circuitry, or each DRAM semiconductor die further comprises a plurality of column address pads and a plurality of row address pads, the plurality of row address pads being physically independent of the plurality of column address pads.
9. 9. The IC stack of claim 7, wherein each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, wherein a bidirectional repeater of a second DRAM semiconductor die is electrically coupled to a corresponding bidirectional repeater of a first DRAM semiconductor die through the second metal line of the laterally extending RDL structure or the upwardly extending RDL structure, and the corresponding bidirectional repeater of the first DRAM semiconductor die is electrically coupled to a corresponding logic I/O pad of the logic control die through the first metal line of the laterally extending RDL structure or the upwardly extending RDL structure.
10. 10. The IC stack of claim 7, wherein each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, wherein a bidirectional repeater of a first DRAM semiconductor die is electrically coupled to a corresponding logic I/O pad of the logic control die through a first metal line of the laterally extending RDL structure or the upwardly extending RDL structure, and a bidirectional repeater of a second DRAM semiconductor die is electrically coupled to a corresponding logic I/O pad of the logic control die through a second metal line of the laterally extending RDL structure or the upwardly extending RDL structure.
11. 11. The IC stack of claim 1, wherein a first IC structure of the plurality of IC structures comprises: A first semiconductor body having a first major surface and a first minor surface, wherein the first major surface is substantially perpendicular to the first minor surface, and An interconnect structure comprising a primary redistribution layer (RDL) over the first major surface, wherein the primary RDL has a second minor surface aligned with the first minor surface of the first semiconductor body; Wherein the first and second minor surfaces together form a minor plane, wherein the primary RDL further includes a first conductive element exposed through the second minor surface of the primary RDL.
12. 12. The IC stack of claim 11, wherein the first conductive element comprises a conductive pad on a surface of the main RDL substantially parallel to the first major surface, a conductive via connecting adjacent layers of the main RDL, a stacked via through the main RDL, or a combination thereof.
13. 13. The IC stack of claim 12, wherein the first semiconductor body further comprises at least one of a through silicon via, a through mold via, or an insulating component exposed through the first minor surface.
14. 14. The IC stack of claim 11, wherein the first semiconductor body comprises a plurality of first dies disposed in a same package layer, vertically stacked second dies disposed side-by-side with other third dies in the same package layer, or a combination thereof.
15. 15. The IC stack of claim 14, wherein the first semiconductor body comprises a plurality of conductive vias, pillars, or plugs of the same or different lengths to electrically connect the plurality of first dies to the main RDL and/or the laterally extending RDL structures.
16. 16. The IC stack of claim 11, wherein the laterally extending RDL structure is electrically connected to the first conductive element of the main RDL, a conductive via, a stud or a plug in the first semiconductor body, or a combination thereof, wherein the laterally extending RDL structure comprises a hybrid bond layer or an array of bump pads.
17. 17. An IC stack, comprising: a plurality of Integrated Circuit (IC) structures horizontally separated from each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four side walls, having a first side wall, a second side wall, a third side wall, and a fourth side wall, wherein the area of the bottom surface or the top surface is larger than the area of any one of the four side walls; a set of upwardly extending thermally conductive layers disposed between any two adjacent ones of the plurality of IC structures, an A first laterally extending thermally conductive layer covering each second sidewall of the plurality of IC structures and thermally coupled to the set of upwardly extending thermally conductive layers.
18. 18. The IC stack of claim 17, further comprising a laterally extending RDL structure covering each first sidewall of the plurality of IC structures.
19. 19. The IC stack of claim 18 wherein each IC structure comprises a DRAM semiconductor die and the IC stack further comprises a logic control die located below and electrically connected to the laterally extending RDL structure of the IC stack, wherein the IC stack is an HBM compliant structure.
20. 20. The IC stack of claim 17, further comprising a second laterally extending thermally conductive layer covering each third sidewall of the plurality of IC structures, wherein the second laterally extending thermally conductive layer is thermally coupled to the set of upwardly extending thermally conductive layers.

Description

Semiconductor package with edge side interconnect and semiconductor package assembly and method of forming the same Technical Field The present disclosure relates generally to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device with side edge interconnects and a method of forming the same. Background Due to the great achievements in engineering and materials science, two-dimensional (2D) geometric scaling of conventional transistors has made great progress involving extremely complex multi-step lithographic patterning, new strain-enhancing materials, and metal oxide gates. However, as the above-described technology approaches its practical limit, 2D device scaling is losing power. Three-dimensional integrated circuit (3D IC) integration, which represents a complete departure from conventional 2D IC integration, has been recognized as a next-generation semiconductor technology that simultaneously achieves high performance, low power consumption, small physical size, and high integration density. The 3DIC provides a way to continuously meet the performance and cost requirements of next-generation devices while still allowing for more relaxed gate lengths and lower process complexity for high-level applications such as high-performance computing (HPC), data centers, and Artificial Intelligence (AI). The 3D IC integration may be performed via: Monolithically integrated and/or Vertical integration of disparate wafers. 3D monolithic integration generally involves vertical integration of multiple active silicon layers and vertical interconnects between layers. Recently, a "Central Processing Unit (CPU) overlaid cache" 3D IC architecture has been demonstrated and commercialized using copper hybrid bonding technology. Today, high Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) stacks, each of which is produced by vertically integrating several DRAM dies on a control IC, represent the highest capacity commercial 3D ICs today. These HBM DRAM stacks are typically mounted side-by-side with the processor ICs on a silicon interposer of a 2.5D IC package (fig. 1A) for high-level applications such as HPC, data center, and AI. 2.5D ICs typically contain Through Silicon Vias (TSVs) in active wafers such as DRAMs and control ICs and silicon intermediaries that may be passive or active. The 2.5D IC may also contain a redistribution layer (RDL) in the interposer and active die. Taking ChatGPT as an example, it is driven by the H100 GPU of nVidia in a 2.5D IC configuration. It is envisioned that in the future, 3D ICs may implement memory-stacked, logic-stacked, and logic-stacked logic structures using interconnect technologies including TSV, RDL containing interconnect wiring and micro-vias, flip-chip bonding based on copper pillar micro-bumps or solder bumps, and emerging copper hybrid bonding technologies. The 3D ICs produced by monolithically and/or isomerically integrated allow heterogeneous wafers and/or active silicon layers from different processes and nodes to be vertically stacked, wafer/die re-used and small wafers in SiP (system in package). Finally, 3D IC integration will enable stacking of HBM DRAM stacks on processors to greatly shorten the data transfer time between DRAM die and processor and greatly reduce peak compute memory bandwidth gap. 3D ICs are well suited for applications that require more transistors to be integrated in a given footprint (e.g., cell phone system single chip, soC) or applications that have broken through the capacity limits of a single chip at the most advanced nodes, such as HPCs, data centers, AI/machine learning, 5G/6G networks, graphics, smart phones/wearable devices, automobiles, and other applications that require ultra-high performance, energy efficient devices. These devices include CPUs, GPUs (graphics processing units), FPGAs (field programmable gate arrays), ASICs (application specific ICs), TPUs (tensor processing units), integrated photonics, APs (mobile application processors), packet buffer/router devices, and the like. To accelerate adoption, 3D IC systems must be designed in an overall fashion via IC package system co-design, which involves silicon IP, IC/die and IC packaging and addresses the attendant power and thermal effect challenges. In contrast to PPAC per square centimeter (performance, power, area, and cost) optimization applied in 2D packaging, IC package system co-design of 3D ICs is intended to achieve "PPAC per cubic millimeter optimization", where the vertical dimensions of the overlay IC, interposer, IC package substrate, IC package, and system Printed Circuit Board (PCB) must be fully considered in all trade-off decisions. Today, all 3D ICs employ a package topology with single side area electrical interconnects, such as from the bottom side of the control IC in the HBM DRAM stack (which is connected to the interposer) to the DRAM die on top of the control IC or from the laminate substrate to