CN-122028775-A - Semiconductor device and method of forming the same

CN122028775ACN 122028775 ACN122028775 ACN 122028775ACN-122028775-A

Abstract

A sacrificial test pad is formed in the semiconductor device for testing operations prior to bonding the semiconductor device with another semiconductor device to form a stacked semiconductor device. The sacrificial test pad may be formed in the interconnect layer and may be formed of a material that enables integration of the sacrificial test pad into a manufacturing process for metallization of the interconnect layer. To prevent or reduce the likelihood that the uneven topography of the sacrificial test pad will degrade the bonding performance of the semiconductor device, a planarization operation may be performed to planarize the surface of the sacrificial test pad. The sacrificial test pad may then be covered by a dielectric layer to reduce the likelihood of oxidation of the sacrificial test pad. The sacrificial test pad is preserved thereby reducing the likelihood of oxidation of the metallization structure beneath the sacrificial test pad. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Inventors

ZHANG YUQI
ZHENG XINLI
SU SHUHUI
JIN HAIGUANG
Xiao qingtai
Wei Yiyang
DENG LIFENG
XU YINGJIE
HUANG SHIFEN

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260512
Application Date: 20251231
Priority Date: 20250410

Claims (10)

1. A method of forming a semiconductor device, comprising: Depositing one or more first dielectric layers over a metallization structure layer in an interconnect layer of a semiconductor device; etching the one or more first dielectric layers to form a recess in the one or more first dielectric layers; A layer of conductive material is deposited in the recess to form a sacrificial test pad in the recess, Wherein the sacrificial test pad is formed over the metallization structures of the plurality of metallization structures; Planarizing the sacrificial test pad, and One or more second dielectric layers are deposited over the sacrificial test pads.
2. The method of claim 1, wherein the layer of conductive material and the metallization structure layer comprise copper (Cu).
3. The method of claim 1, further comprising: A conformal barrier layer is deposited in the recess, Wherein depositing the layer of conductive material in the recess to form the sacrificial test pad comprises: depositing the conductive material layer over the conformal barrier layer in the recess to form the sacrificial test pad.
4. A method according to claim 3, further comprising: Etching the one or more second dielectric layers to form dual damascene recesses in the one or more second dielectric layers, and Another layer of conductive material is deposited in the dual damascene recess to form bond interconnects and bond pads in the dual damascene recess, Wherein the bottom surface of the bond pad extends into at least one of the one or more first dielectric layers.
5. The method of claim 4, wherein a top surface of the sacrificial test pad is higher than the bottom surface of the bond pad in the semiconductor device.
6. The method of claim 1, further comprising: Etching the one or more second dielectric layers to form dual damascene recesses in the one or more second dielectric layers, and Another layer of conductive material is deposited in the dual damascene recess to form bond interconnects and bond pads in the dual damascene recess, Wherein the bottom surface of the bond pad and the top surface of the sacrificial test pad are coplanar.
7. The method of claim 1, wherein after planarizing the sacrificial test pad, the sacrificial test pad has a thickness greater than about 1 angstrom and less than about 10000 angstroms.
8. A method of forming a semiconductor device, comprising: Depositing one or more first dielectric layers over a metallization structure layer in an interconnect layer of a semiconductor device; etching the one or more first dielectric layers to form a recess in the one or more first dielectric layers; Depositing a layer of conductive material in the recess; Performing a first planarization operation to planarize the layer of conductive material to form sacrificial test pads in the recesses, Wherein the sacrificial test pad is formed over the metallization structures of the plurality of metallization structures; Applying one or more test probes to the sacrificial test pads to test the semiconductor device; Performing a second planarization operation to planarize the sacrificial test pad, and One or more second dielectric layers are deposited over the sacrificial test pads.
9. The method of claim 8, wherein performing the second planarization operation comprises: the planarization operation is performed after the one or more test probes are applied to the sacrificial test pads to test the semiconductor device.
10. A semiconductor device, comprising: A device layer; A plurality of transistors in the device layer, Wherein at least one of the plurality of transistors comprises: A channel layer; a gate structure adjacent to at least three sides of the channel layer, and A gate dielectric layer between the channel layer and the gate structure; an interconnect layer over the plurality of transistors, comprising: a plurality of dielectric layers; A plurality of metallization structure layers disposed in the plurality of dielectric layers, Wherein the plurality of metallization structure layers are spaced apart from each other by the plurality of dielectric layers, and Wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constants of the plurality of dielectric layers; a passivation layer over the plurality of metallization structure layers; A bonding interconnect in the passivation layer, and And the copper test pad is positioned in the passivation layer.

Description

Semiconductor device and method of forming the same Technical Field Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Various semiconductor device packaging techniques may be used to incorporate one or more semiconductor die into a semiconductor package. In some cases, semiconductor devices may be stacked in a semiconductor package to achieve a smaller horizontal or lateral footprint of the semiconductor package and/or to increase the density of the semiconductor package. Semiconductor device packaging techniques that may be implemented for integrating multiple semiconductor devices in a semiconductor package may include integrated fan-out (InFO), package-on-package (PoP), chip-on-wafer (CoW), wafer-on-wafer (WoW), and/or chip-on-substrate (CoWoS), among other examples. Disclosure of Invention Some embodiments of the present application provide a method of forming a semiconductor device comprising depositing one or more first dielectric layers over a metallization structure layer in an interconnect layer of the semiconductor device, etching the one or more first dielectric layers to form a recess in the one or more first dielectric layers, depositing a layer of conductive material in the recess to form a sacrificial test pad in the recess, wherein the sacrificial test pad is formed over the metallization structures of the plurality of metallization structures, planarizing the sacrificial test pad, and depositing one or more second dielectric layers over the sacrificial test pad. Further embodiments of the present application provide a method of forming a semiconductor device comprising depositing one or more first dielectric layers over a metallization structure layer in an interconnect layer of the semiconductor device, etching the one or more first dielectric layers to form a recess in the one or more first dielectric layers, depositing a layer of conductive material in the recess, performing a first planarization operation to planarize the layer of conductive material to form a sacrificial test pad in the recess, wherein the sacrificial test pad is formed over the metallization structures of the plurality of metallization structures, applying one or more test probes to the sacrificial test pad to test the semiconductor device, performing a second planarization operation to planarize the sacrificial test pad, and depositing one or more second dielectric layers over the sacrificial test pad. Still further embodiments of the present application provide a semiconductor device comprising a device layer, a plurality of transistors in the device layer, wherein at least one of the plurality of transistors comprises a channel layer, a gate structure adjacent to at least three sides of the channel layer, and a gate dielectric layer between the channel layer and the gate structure, an interconnect layer over the plurality of transistors comprising a plurality of dielectric layers, a plurality of metallization structure layers disposed in the plurality of dielectric layers, wherein the plurality of metallization structure layers are spaced apart from each other by the plurality of dielectric layers, and wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the plurality of dielectric layers, a passivation layer over the plurality of metallization structure layers, a bonding interconnect in the passivation layer, and a copper test pad in the passivation layer. Drawings The various aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1A and 1B are diagrams of exemplary stacked semiconductor devices described herein. Fig. 2A and 2B are diagrams of exemplary embodiments of test pads that may be included in the semiconductor devices described herein. Fig. 3 is a diagram of an exemplary embodiment of a test pad that may be included in the semiconductor devices described herein. Fig. 4A and 4B are diagrams of exemplary embodiments of test pads that may be included in the semiconductor devices described herein. Fig. 5A and 5B are diagrams of exemplary embodiments of test pads that may be included in the semiconductor devices described herein. Fig. 6 is a diagram of an exemplary embodiment of a process for forming a stacked semiconductor device described herein. Fig. 7A through 7P are diagrams of forming exemplary embodiments of semiconductor devices described herein. Fig. 8A and 8B are diagrams of forming an exemplary embodiment of a stacked semiconductor device described herein. Fig. 9 is a flow chart of an exemplary process associated with forming a semiconductor device de