CN-122028776-A - Fan-out type packaging structure and preparation method thereof

Abstract

The embodiment of the application provides a fan-out type packaging structure and a preparation method thereof, relates to the technical field of semiconductor packaging, and is used for solving the problem of packaging layer fracture filled around a first chip and the problem of delamination and fracture of a rewiring layer. The fan-out type packaging structure comprises a rewiring layer, a first chip, a first connecting piece, a first supporting layer and a packaging layer. The first chip is electrically connected to the rewiring layer through the first connection. A first support layer is disposed between the first chip and the rewiring layer and in contact with the rewiring layer. The packaging layer is filled around the first chip, and the packaging layer wraps the first chip, the first connecting piece and the first supporting layer.

Inventors

• JING XIANGMENG
• GUO MAO
• GENG YUJIE
• JIANG QINGQING
• HONG RUIBIN
• ZHAO NAN

Assignees

• 华为技术有限公司

Dates

Publication Date

20260512

Application Date

20200911

Claims (19)

1. 1. A fan-out package structure, comprising: Rewiring layers; a first chip; the first chip is electrically connected with the rewiring layer through the first connecting piece; a first support layer disposed between the first chip and the rewiring layer and in contact with the rewiring layer; The packaging layer is filled around the first chip; the packaging layer wraps the first chip, the first connecting piece and the first supporting layer; The fan-out package structure further comprises a second chip; The first support layer includes a first support portion located in an area between the first chip and the second chip.
2. 2. The fan-out package structure of claim 1, wherein the first support layer comprises a first support portion that surrounds the first chip.
3. 3. The fan-out type package structure according to claim 1 or 2, wherein the first supporting layer further comprises a second supporting portion, wherein the second supporting portion comprises a plurality of first supporting bars arranged in parallel and a plurality of second supporting bars arranged in parallel; The second support portion is located directly below the first chip, and an orthographic projection of the first connection member on the rewiring layer and an orthographic projection of the second support portion on the rewiring layer have no overlapping area.
4. 4. The fan-out package structure of claim 1, further comprising a second support layer disposed on a side of the first support layer remote from the rewiring layer and in contact with the first support layer; The second support layer includes a third support portion located in an area between the first chip and the second chip.
5. 5. The fan-out package structure of claim 2, further comprising a second support layer disposed on a side of the first support layer remote from the rewiring layer and in contact with the first support layer; the second support layer includes a third support portion that surrounds the first chip.
6. 6. The fan-out package structure of any one of claims 3-5, further comprising a second support layer disposed on a side of the first support layer away from the rewiring layer and in contact with the first support layer; the second supporting layer comprises a fourth supporting part, wherein the fourth supporting part comprises a plurality of third supporting strips which are arranged in parallel and a plurality of fourth supporting strips which are arranged in parallel; The fourth support portion is located directly below the first chip, and an orthographic projection of the first connection member on the rewiring layer and an orthographic projection of the fourth support portion on the rewiring layer have no overlapping area.
7. 7. The fan-out package structure of claim 1, wherein the rewiring layer comprises a first conductive contact; the first connecting piece is electrically connected with the first conductive contact; the first support layer is of the same material as the first conductive contact.
8. 8. The fan-out package structure of claim 1, further comprising an adhesive layer disposed between the first support layer and the rewiring layer.
9. 9. The fan-out package structure of claim 1, wherein the first support layer is electrically conductive; The first support layer is electrically connected to the ground terminal in the rewiring layer.
10. 10. The fan-out package structure of claim 1, wherein the material strength of the first support layer is greater than the material strength of the package layer.
11. 11. The fan-out package structure of claim 1, further comprising a second connector and a substrate disposed on a side of the rewiring layer remote from the first chip, the second connector electrically connecting the rewiring layer to the substrate.
12. 12. The fan-out package structure of claim 1, wherein the material of the encapsulation layer comprises a molding compound; the packaging layer comprises a first sub-packaging layer and a second sub-packaging layer, the first sub-packaging layer surrounds the first chip, the second sub-packaging layer surrounds the first sub-packaging layer, the material of the first sub-packaging layer is a primer compound, and the material of the second sub-packaging layer is a molding compound.
13. 13. An electronic device, comprising the fan-out package structure of any one of claims 1-12 and a printed circuit board; The fan-out type packaging structure comprises a substrate and a third connecting piece, wherein the third connecting piece is arranged on one side, far away from the rewiring layer, of the substrate, and the substrate is electrically connected with the printed circuit board through the third connecting piece.
14. 14. The preparation method of the fan-out type packaging structure is characterized by comprising the following steps of: forming a first support layer on the rewiring layer; Binding a first chip to the rewiring layer by a first connector to electrically connect the first chip with the rewiring layer; and filling an encapsulation layer, wherein the encapsulation layer wraps the first chip, the first connecting piece and the first supporting layer.
15. 15. The method of manufacturing a fan-out package structure of claim 14, wherein forming a first support layer on the rewiring layer comprises: forming an electroplating seed layer on the rewiring layer; Forming a photoresist layer on the electroplating seed layer, wherein the photoresist layer is hollowed out in a region where the first supporting layer is to be formed; electroplating in the hollowed-out area of the photoresist layer to form the first supporting layer; and removing the photoresist layer and the electroplating seed layer below the photoresist layer.
16. 16. The method of manufacturing a fan-out package structure of claim 14, wherein forming a first support layer on the rewiring layer comprises: forming a support film on a carrier plate; attaching a glue film on the support film; Patterning the support film and the adhesive film to form a first support layer and an adhesive layer, wherein orthographic projections of the first support layer and the adhesive layer on the carrier plate are overlapped; and moving the first supporting layer and the adhesive layer onto the rewiring layer, and removing the carrier plate, wherein the first supporting layer is adhered onto the rewiring layer through the adhesive layer.
17. 17. The method of manufacturing a fan-out package structure of claim 14, wherein forming a first support layer on the rewiring layer comprises: And forming the first supporting layer on the rewiring layer, and synchronously forming a first conductive contact of the rewiring layer, wherein the first connecting piece is electrically connected with the first conductive contact.
18. 18. The method of manufacturing a fan-out package structure of claim 14, wherein the filling the package layer comprises: filling the packaging layer through a plastic mold bottom filling process; or filling a first sub-packaging layer through a capillary underfill process, wherein the first sub-packaging layer surrounds the first chip; and filling a second sub-packaging layer through a plastic mold bottom filling process, wherein the second sub-packaging layer surrounds the first sub-packaging layer, and the packaging layer comprises the first sub-packaging layer and the second sub-packaging layer.
19. 19. The method of manufacturing a fan-out package structure of claim 14, wherein after filling the package layer, the method of manufacturing a fan-out package structure further comprises: and forming a second connecting piece electrically connected with the rewiring layer on one side of the rewiring layer away from the first chip, and electrically connecting the second connecting piece with the substrate.

Description

Fan-out type packaging structure and preparation method thereof The present application is a divisional application, the application number of the original application is 202080104737.1, the original application date is 2020, 09, 11, and the whole content of the original application is incorporated by reference. Technical Field The application relates to the technical field of semiconductor packaging, in particular to a fan-out type packaging structure and a preparation method thereof. Background In recent years, the development of integrated circuits has entered the ultra-large scale integrated circuit era. Packaging of integrated circuits has evolved to higher density, higher speed, lower cost, and more reliable. Current packaging methods include stack packaging (package on package, POP), flip chip (flip chip), fan Out Package (FOP), and the like. Wherein, interconnection between the first chip (die) and the substrate in the fan-out type packaging structure is realized through a re-wiring layer (re-distribution layer, RDL), so that the interconnection density can be increased and the bandwidth can be increased. However, since the thermal expansion coefficient (coefficient of thermal expansion, CTE) of the first chips in the fan-out package structure is low and the thermal expansion coefficient of the substrate is high, in an environment with temperature change, the package structure is prone to the problem that the package layer such as Underfill (UF) filled in the area between two adjacent first chips is broken due to the mismatch of the thermal expansion coefficients, and in severe cases, delamination (delamination) and breakage of the rewiring layer occur due to the fact that the insulation layer (the material of the insulation layer may be Polyimide (PI)) in the rewiring layer. In addition, the thickness of the rewiring layer is small, the strength in the fan-out type packaging structure is low, and reliability problems such as self-fracture of the rewiring layer or fracture of the rewiring layer caused by other failures are easy to occur. Disclosure of Invention The embodiment of the application provides a fan-out type packaging structure and a preparation method thereof, which are used for solving the problem of fracture caused by mismatch of thermal expansion coefficients of packaging layers filled around a first chip and the problem of delamination and fracture of a rewiring layer. In order to achieve the above purpose, the application adopts the following technical scheme: In a first aspect, a fan-out package structure is provided. The fan-out type packaging structure comprises a rewiring layer, a first chip, a first connecting piece, a first supporting layer, a packaging layer and a first supporting layer, wherein the first chip is electrically connected with the rewiring layer through the first connecting piece, the first supporting layer is arranged between the first chip and the rewiring layer and is in contact with the rewiring layer, the packaging layer is filled around the first chip, and the packaging layer wraps the first chip, the first connecting piece and the first supporting layer. Because the first supporting layer is arranged between the first chip and the rewiring layer, the first supporting layer can increase the structural strength of a local area, reduce the stress generated by unmatched thermal expansion coefficients of different parts of the packaging layer filled around the first chip due to fan-out type packaging structure, avoid the breakage of the packaging layer filled around the first chip, avoid the breakage of the rewiring layer and the delamination phenomenon of the rewiring layer, and improve the overall reliability of the fan-out type packaging structure. In one possible implementation, the material strength of the first support layer provided in the fan-out package structure is greater than the material strength of the package layer. This ensures that the first support layer is able to act as a support. In addition, when the fan-out package structure does not include the first supporting layer, the first chip and the rewiring layer are supported by the packaging layer, and because the first supporting layer is arranged in the embodiment of the application, the thickness of the packaging layer filled between the first chip and the rewiring layer can be reduced, namely, the thickness of the whole packaging layer is reduced, and the thickness of the fan-out package structure can be controlled by adjusting the thickness of the first supporting layer. Compared with the fan-out type packaging structure with the thickness of the fan-out type packaging structure adjusted by other methods, for example, the thickness of the first chip is adjusted to adjust the thickness of the fan-out type packaging structure. In one possible embodiment, the fan-out package structure further includes a second chip, and the first support layer includes a first support portion located in a re