CN-122028781-A - Semiconductor device and preparation method thereof

CN122028781ACN 122028781 ACN122028781 ACN 122028781ACN-122028781-A

Abstract

The application provides a semiconductor device and a preparation method thereof, relating to the technical field of semiconductors, wherein the preparation method of the semiconductor device comprises the steps of forming a passive device part, wherein the passive device part comprises a plurality of passive device areas; and forming a transistor part, wherein the transistor part comprises a plurality of heterojunction bipolar transistor devices, the transistor part is connected with the passive device part, and the heterojunction bipolar transistor devices respectively correspond to a plurality of passive device areas. Through wafer-level flip-chip bonding between the transistor part and the passive device part, corresponding interconnection of a plurality of heterojunction bipolar transistor devices and passive device structures of a plurality of passive device areas is realized, the device size is reduced, the integration level is improved, and chip miniaturization is facilitated.

Inventors

PAN LIN
ZHOU YI
QIAN KANG
WU XIANGHUI

Assignees

常州承芯半导体有限公司

Dates

Publication Date: 20260512
Application Date: 20260213

Claims (13)

1. A method of manufacturing a semiconductor device, comprising: Forming a first bonding pad, a second bonding pad, a third bonding pad and a capacitor structure on the passive device region, wherein the second bonding pad is electrically connected with the capacitor structure; Forming a transistor portion including providing a second wafer, forming a plurality of heterojunction bipolar transistor devices, and bonding the plurality of heterojunction bipolar transistor devices on a predetermined location of the second wafer, wherein forming the heterojunction bipolar transistor devices includes providing a substrate, forming a device structure on the substrate, the device structure including a first collector electrode, a first base electrode, and a first emitter electrode, forming a first interconnect metal structure on the substrate, the first interconnect metal structure being electrically connected to the first collector electrode, forming a second interconnect metal structure on the substrate, the second interconnect metal structure being electrically connected to the first base electrode, and forming a third interconnect metal structure on the substrate, the third interconnect metal structure being electrically connected to the first emitter electrode; And bonding the transistor part and the passive device part, wherein a plurality of heterojunction bipolar transistor devices respectively correspond to a plurality of passive device regions, the first interconnection metal structure is correspondingly bonded with the first bonding pad, the second interconnection metal structure is correspondingly bonded with the second bonding pad, and the third interconnection metal structure is correspondingly bonded with the third bonding pad.
2. The method of manufacturing a semiconductor device of claim 1, wherein forming the first interconnect metal structure comprises forming a first stud on the substrate, forming a first interconnect metal layer overlying the first stud, the first interconnect metal layer being connected to the first collector; forming the second interconnection metal structure comprises forming a second convex column on the substrate; forming a second interconnection metal layer covering the second convex column, wherein the second interconnection metal layer is connected with the first base electrode; The forming of the third interconnection metal structure comprises forming a third convex column on the substrate and forming a third interconnection metal layer covering the third convex column, wherein the third interconnection metal layer is connected with the first emission electrode.
3. The method of manufacturing a semiconductor device according to claim 1, wherein forming the passive device portion further comprises forming a fourth pad for collector voltage input and a first wiring layer connecting the first pad and the fourth pad on the passive device region.
4. The method of manufacturing a semiconductor device according to claim 1, wherein forming the passive device portion further comprises forming a fifth pad for radio frequency signal input and a second wiring layer connecting the capacitor structure and the fifth pad on the passive device region.
5. The method of manufacturing a semiconductor device according to claim 2, wherein forming the heterojunction bipolar transistor device further comprises forming a fourth interconnect metal structure on the substrate, the fourth interconnect metal structure being electrically connected to the first base electrode; forming a sixth bonding pad on the passive device region, wherein the sixth bonding pad is used for inputting a base DC bias voltage; Bonding the transistor portion with the passive device portion further includes correspondingly bonding the fourth interconnect metal structure with the sixth pad.
6. The method of manufacturing a semiconductor device according to claim 5, wherein forming the fourth interconnect metal structure comprises forming a fourth stud on the substrate, and forming a fourth interconnect metal layer over the fourth stud, the fourth interconnect metal layer being connected to the first base electrode.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the first pillar, the second pillar, the third pillar, and the fourth pillar have a first height, and the device structure has a second height, the first height being greater than the second height.
8. The method of manufacturing a semiconductor device according to claim 7, wherein a ratio of the first height to the second height is in a range of 2:1 to 6:1.
9. The method of manufacturing a semiconductor device according to claim 1, wherein forming the passive device portion further comprises forming an interconnect via in the passive device region, the interconnect via being for grounding through the first wafer, the interconnect via being electrically connected to the third interconnect metal structure.
10. The method for manufacturing a semiconductor device according to claim 6, wherein the materials of the first pillar, the second pillar, the third pillar, and the fourth pillar include poly-p-phenylene benzobisoxazole.
11. The method of manufacturing a semiconductor device according to claim 1, wherein forming the passive device portion further comprises forming an eighth pad and a ninth pad on the passive device region; The heterojunction bipolar transistor device further comprises a second collector electrode, a second base electrode, a second emission electrode, a fifth interconnection metal structure, a sixth interconnection metal structure, a third interconnection metal structure, a fourth interconnection metal structure and a third interconnection metal structure, wherein the fifth interconnection metal structure is positioned on the substrate and is electrically connected with the second collector electrode; The fifth interconnect metal structure is correspondingly bonded to the eighth pad, and the sixth interconnect metal structure is correspondingly bonded to the ninth pad.
12. The method of manufacturing a semiconductor device according to claim 1, wherein after bonding the transistor portion and the passive device portion, comprising removing the second wafer, dicing the passive device portion to obtain a plurality of the semiconductor devices.
13. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 12.

Description

Semiconductor device and preparation method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background In modern wireless communication systems, the rf front-end module is a core part for implementing signal transceiving, and its performance directly determines the quality and efficiency of wireless communication. The rf front-end module generally includes key devices such as filters, amplifiers, bipolar devices, antenna switches, etc., and each device together forms a signal receiving and transmitting link. In the transmitting chain, the Power Amplifier (PA) is responsible for amplifying the signal output by the radio frequency transceiver to drive the antenna and realize effective signal radiation, so that the performance of the power amplifier, such as output power, linearity, efficiency and reliability, is a key factor affecting the overall performance of the communication device. Currently, power amplifiers employed in communication devices may be largely classified into Field Effect Transistor (FET) based power amplifiers and bipolar transistor (BJT) based power amplifiers according to their core device structures. Heterojunction Bipolar Transistor (HBT) is used as a special type bipolar transistor, and has remarkable advantages of high current density, high power gain, good linearity, easiness in monolithic integration and the like, so that the heterojunction bipolar transistor is widely applied to the field of radio frequency power amplifiers, and particularly in application scenes with strict requirements on high frequency and high efficiency. HBT power amplifier chips (HBT PA chips) have become one of the mainstream solutions for transmit chain front-end modules in modern mobile communication, satellite communication, wireless local area network, etc. systems. The existing HBT PA chip has limitations in device structure, material system or manufacturing process, and innovative improvement is needed to develop the improvement of the integration level on the premise of ensuring the performance and the reliability so as to meet the requirement of gradually miniaturizing the wireless communication equipment. Disclosure of Invention The application provides a semiconductor device and a preparation method thereof, which improve the integration level and are beneficial to chip miniaturization. In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows: In one aspect of the embodiment of the application, a preparation method of a semiconductor device is provided, which comprises the steps of forming a passive device part, providing a first wafer, wherein the first wafer comprises a plurality of passive device areas, forming a first bonding pad, a second bonding pad, a third bonding pad and a capacitor structure on the passive device areas, and electrically connecting the second bonding pad with the capacitor structure; forming a transistor portion including providing a second wafer, forming a plurality of heterojunction bipolar transistor devices, and bonding the plurality of heterojunction bipolar transistor devices on a predetermined location of the second wafer, wherein forming the heterojunction bipolar transistor devices includes providing a substrate, forming a device structure on the substrate, the device structure including a first collector electrode, a first base electrode, and a first emitter electrode, forming a first interconnect metal structure on the substrate, the first interconnect metal structure being electrically connected to the first collector electrode, forming a second interconnect metal structure on the substrate, the second interconnect metal structure being electrically connected to the first base electrode, and forming a third interconnect metal structure on the substrate, the third interconnect metal structure being electrically connected to the first emitter electrode; And bonding the transistor part and the passive device part, wherein the heterojunction bipolar transistor devices respectively correspond to the passive device regions, the first interconnection metal structure is correspondingly bonded with the first bonding pad, the second interconnection metal structure is correspondingly bonded with the second bonding pad, and the third interconnection metal structure is correspondingly bonded with the third bonding pad. In some possible embodiments, forming the first interconnect metal structure includes forming a first stud on the substrate, forming a first interconnect metal layer overlying the first stud, the first interconnect metal layer being connected to the first collector; Forming a second interconnection metal structure including forming a second stud on the substrate, forming a second interconnection metal layer covering the second stud, the second interconnection metal layer being connec