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CN-122028782-A - Chip packaging structure, adapter plate, manufacturing method of adapter plate and electronic equipment

CN122028782ACN 122028782 ACN122028782 ACN 122028782ACN-122028782-A

Abstract

A chip packaging structure, an adapter plate, a preparation method thereof and electronic equipment are provided, and relate to the technical field of semiconductor packaging. The chip packaging structure comprises a plurality of chips, a first adapter plate and a second adapter plate which are arranged in a stacked mode. The first adapter plate is bonded to one side of the chips and is internally provided with a conductive device. The second adapter plate is positioned at one side of the first adapter plate far away from the chips, a first flow passage and a plurality of conductive columns are arranged in the second adapter plate, and part of the first flow passage is positioned between the adjacent conductive columns. Therefore, the cooling substance in the first runner can radiate the heat of the conductive device in the first adapter plate, the conductive column in the second adapter plate and the chips, and the radiating effect is improved. The conductive posts penetrate through the second adapter plate along the thickness direction of the second adapter plate, and the conductive posts can be used for realizing the coupling of a plurality of chips, conductive devices and other components (such as a substrate).

Inventors

  • JIANG SHANGXUAN
  • ZHAO NAN
  • XU JIKAI
  • YU ZIBIN
  • TANG JIAJIE

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260512
Application Date
20251231

Claims (18)

  1. 1. A chip package structure, comprising: a plurality of chips stacked; The first adapter plate is bonded to one side of the chips and internally provided with a conductive device; The first transfer plate is positioned at one side of the first transfer plate far away from the chips, and is internally provided with a first flow passage and a plurality of conductive columns, and part of the first flow passage is positioned between the adjacent conductive columns; the conductive column penetrates through the second adapter plate along the thickness direction of the second adapter plate, and one end of the conductive column is coupled with the conductive device.
  2. 2. The chip package structure of claim 1, wherein the conductive device comprises an active device; the active surface of the active device faces the second adapter plate.
  3. 3. The chip package structure of claim 1 or 2, wherein the conductive device comprises a passive device and a redistribution layer coupled; The rewiring layer is located between the passive device and the second interposer.
  4. 4. The chip package structure of any of claims 1-3, wherein the conductive device comprises an active device and the passive device; the arrangement density of the first flow channels, which are arranged opposite to the active devices, is greater than that of the first flow channels, which are arranged opposite to the passive devices.
  5. 5. The chip package structure of claim 4, wherein the second interposer further comprises: The first opening and the second opening are both positioned on one side of the second adapter plate, which faces the first adapter plate, and are communicated with the first flow channel.
  6. 6. The chip package structure of claim 5, wherein an orthographic projection of the first interposer on the second interposer does not overlap with the first opening and the second opening.
  7. 7. The chip package structure according to claim 5 or 6, wherein the first flow path disposed opposite to the active device is closer to the first opening than the first flow path disposed opposite to the passive device, the first opening serving as a cold liquid inlet.
  8. 8. The chip package structure of any one of claims 1-7, wherein the second interposer includes a cover and a cavity, the conductive pillars including first and second conductive pillars; the first conductive column penetrates through the cover body, and the second conductive column penetrates through the cavity body; the cover body is in fusion bonding with the cavity, and the first conductive column is in fusion bonding with the second conductive column.
  9. 9. The chip packaging structure according to any one of claims 1 to 8, further comprising: and the heat dissipation structure is positioned at one side of the chip away from the first adapter plate.
  10. 10. The chip package structure of claim 6, wherein the heat dissipation structure comprises a second flow channel; The chip package structure further includes a third opening configured to provide a cooling liquid to the first and second flow channels and a fourth opening configured to receive the liquid output by the first and second flow channels.
  11. 11. The chip package structure according to any one of claims 1-10, wherein the second interposer further comprises a dielectric structure; At least part of the dielectric structure is positioned between the conductive post and the first flow channel, and the material of the dielectric structure comprises one or more of glass, silicon or ceramic.
  12. 12. The chip package structure of claim 11, wherein the second interposer further comprises a cover layer; The cover layer is positioned between the dielectric structure and the first flow channel, and the material of the cover layer comprises one or more of glass, silicon, ceramic or metal.
  13. 13. The chip package structure of any of claims 2, 4-6, wherein the active device comprises one or more of an integrated voltage regulator, a transistor, or an optoelectronic device.
  14. 14. The chip package structure of any of claims 3, 4-6, wherein the passive device comprises one or more of a copper pillar, an inductor, a capacitor, or a resistor.
  15. 15. The adapter plate is characterized by comprising a medium structure, a runner and a plurality of conductive columns; at least part of the medium structure is positioned between the runner and the conductive posts, and part of the runner is positioned between adjacent conductive posts; The conductive posts extend along the thickness direction of the adapter plate, and the top surfaces and the bottom surfaces of the conductive posts are exposed.
  16. 16. An electronic device comprising a circuit board and the chip package structure of any one of claims 1-14; The chip packaging structure is positioned on the circuit board and coupled with the circuit board.
  17. 17. The preparation method of the adapter plate is characterized by comprising the following steps of: forming a cover body and a first conductive column, wherein the first conductive column penetrates through the cover body along the thickness direction; forming a cavity and a second conductive column, wherein the second conductive column penetrates through the cavity along the thickness direction; And bonding the cover body, the cavity, the first conductive column and the second conductive column.
  18. 18. The method of manufacturing according to claim 17, wherein the bonding process comprises fusion bonding.

Description

Chip packaging structure, adapter plate, manufacturing method of adapter plate and electronic equipment Technical Field The embodiment of the application relates to the technical field of semiconductor packaging, in particular to a chip packaging structure, an adapter plate, a preparation method of the adapter plate and electronic equipment. Background Under the development of market diversification, emerging applications such as artificial intelligence, big data, cloud computing and the like are emerging, and the application scenes have unprecedented high requirements on the performance of electronic equipment. The performance of the chip packaging structure as a key component in the electronic device can be directly influenced by the performance of the electronic device. At present, the chip packaging structure needs to continuously integrate conductive devices (such as active devices or passive devices) to meet the increasingly abundant performance demands of users, and the heat productivity in the chip packaging structure is rapidly accumulated, so that the problems of local overheating and the like are easy to occur. Therefore, the heat dissipation problem gradually becomes a key factor for limiting the release of the chip performance. Disclosure of Invention The embodiment of the application provides a chip packaging structure, an adapter plate, a preparation method of the adapter plate and electronic equipment, which are used for improving the heat dissipation performance of the chip packaging structure. In a first aspect, a chip package structure is provided. The chip packaging structure comprises a plurality of chips, a first adapter plate and a second adapter plate. The plurality of chips are stacked. The first adapter plate is bonded to one side of the chips and is arranged below the chips. The first adapter plate is internally provided with a conductive device, and the conductive device in the first adapter plate can be electrically connected with a plurality of chips. The second adapter plate is positioned on one side of the first adapter plate away from the chips. The second adapter plate is internally provided with a first flow passage and a plurality of conductive posts, part of the first flow passage is positioned between the adjacent conductive posts, and the first flow passage can be arranged in a semi-circular manner around the plurality of conductive posts. The conductive columns penetrate through the second adapter plate along the thickness direction of the second adapter plate, one ends of the conductive columns are coupled with the conductive devices, namely, the plurality of chips, the conductive devices in the first adapter plate and the conductive columns in the second adapter plate can be electrically connected. In the chip packaging structure provided by the embodiment of the application, the conductive device (such as an active device or a passive device) in the first adapter plate can generate heat in the working process, the second adapter plate is arranged on one side of the first adapter plate, the cooling substance can flow in the first flow channel of the second adapter plate, and the heat generated by the conductive device can be transferred to the cooling substance, so that the rapid heat dissipation of the conductive device is realized, the situation that the first adapter plate is locally overheated is reduced or avoided, and the performance release of the conductive device is promoted. From another angle, the conductive device can dissipate heat rapidly, heat accumulation in the first adapter plate can be reduced, and the heat transfer to the chips in the first adapter plate can be avoided, so that performance release of the chips is prevented from being influenced. In addition, the conductive columns can realize the electric connection of a plurality of chips, conductive devices and other components (such as a substrate), heat can be generated in the working process of the conductive columns, part of the first flow channels are arranged between the adjacent conductive columns, the distance between the conductive columns and cooling substances in the first flow channels is extremely short, and the rapid heat dissipation of the conductive columns can be promoted. In addition, the heat generated by the chips can be downwards transferred, and then the heat dissipation is realized through the cooling substances in the first flow channel. For example, the active surfaces of the chips are usually oriented to the second adapter plate, and the area where the active surfaces are located generally generates more heat in the working process, and the heat can be transferred to the first adapter plate and then transferred to the second adapter plate, so that the cooling substance in the first flow channel can realize heat dissipation of the chips, and is beneficial to promoting performance release of the chips. In one possible implementation, the conductive device comprises an ac