CN-122028783-A - Packaging method and packaging structure of semiconductor chip

Abstract

The invention provides a packaging method and a packaging structure of a semiconductor chip, which are provided with a substrate and at least one semiconductor chip arranged on the substrate, wherein a bonding pad of the semiconductor chip is electrically communicated with the substrate, the substrate is electrically communicated with the outside, the bonding pad of the semiconductor chip is further provided with an upward connection structure so as to realize direct electrical communication of the semiconductor chip with the outside, the semiconductor chip forms a double-sided communication packaging form, a plurality of signal transmission channels are formed between the semiconductor chip and the outside, thereby reducing the wiring difficulty of the substrate, saving the area and the layer number of the substrate, facilitating the adjustment of the size of the substrate to enable the substrate to be matched with the sizes of other components, improving the signal transmission speed and quality, improving the performance of the packaging structure and reducing the overall cost.

Inventors

• XIA HUAN

Assignees

• 格科微电子（上海）有限公司

Dates

Publication Date

20260512

Application Date

20241101

Claims (20)

1. 1. A method of packaging a semiconductor chip, comprising: Providing a substrate and at least one semiconductor chip arranged on the substrate; the bonding pad of the semiconductor chip is electrically communicated with the substrate, and the substrate is electrically communicated with the outside; the bonding pad of the semiconductor chip is also provided with an upward connection structure so as to realize direct electrical communication between the semiconductor chip and the outside.
2. 2. The method of packaging a semiconductor chip as claimed in claim 1, wherein the structure of the upward connection of the semiconductor chip includes connection by a metal wire.
3. 3. The method of packaging a semiconductor chip of claim 2, wherein the substrate in electrical communication with the exterior comprises an upwardly connected structure and a downwardly connected structure, the upwardly connected structure of the substrate comprising a connection by a metal line.
4. 4. The packaging method of a semiconductor chip according to claim 1, wherein the semiconductor chip is an image signal processing chip, a pad of the image signal processing chip is connected to the substrate through a first via, the substrate is connected to one of an external image sensor chip assembly or a connector through an upwardly connected second via and is connected to the other of the image sensor chip assembly or the connector through a downwardly connected fourth via, and the pad of the image signal processing chip is further connected to the one of the image sensor chip assembly or the connector through an upwardly connected third via.
5. 5. The packaging method of semiconductor chips as defined in claim 1, wherein at least two semiconductor chips are stacked on the substrate, wherein each semiconductor chip is provided with an upward connection structure to enable the semiconductor chips to be directly electrically connected to the outside.
6. 6. The method of packaging semiconductor chips as recited in claim 5, wherein said at least two semiconductor chips include an image signal processing chip and a memory chip.
7. 7. The method of packaging a semiconductor chip of claim 4, wherein the substrate includes opposing first and second surfaces, the image signal processing chip is secured to the first surface of the substrate and covered with a layer of injection molding material, the layer of injection molding material has a redistribution layer disposed thereon, the redistribution layer is coupled to one of the image sensor chip assembly or the connector, and the second surface of the substrate is coupled to the other of the image sensor chip assembly or the connector.
8. 8. The method of packaging a semiconductor chip according to claim 7, wherein the first via includes a first metal line having one end connected to a first pad of the substrate and the other end connected to a pad of the image signal processing chip.
9. 9. The method of packaging a semiconductor chip according to claim 8, wherein the wire bonding direction of the first metal wire is wire bonding from the first pad of the substrate to the pad of the image signal processing chip to reduce the height of the first metal wire.
10. 10. The method of packaging a semiconductor chip according to claim 8, wherein the second via includes a first metal ball, a metal post, a via filled with a metal layer, or a second metal line, one end of the first metal ball, the metal post, the via filled with the metal layer, or the second metal line is connected to the second pad of the substrate, and the other end is connected to the rewiring layer.
11. 11. The method of packaging a semiconductor chip as claimed in claim 10, wherein the second metal wire is connected to the second bonding pad of the substrate at both ends by wire bonding before the injection molding material layer is formed, and the second metal wire is cut and exposed by thinning the injection molding material layer after the injection molding material layer is formed.
12. 12. The method of packaging a semiconductor chip as claimed in claim 10, wherein the first metal balls or metal pillars are connected to the second pads of the substrate by soldering or surface mounting before the injection molding material layer is formed, and the first metal balls or metal pillars are exposed by thinning the injection molding material layer after the injection molding material layer is formed.
13. 13. The packaging method of a semiconductor chip according to claim 10, wherein after the injection molding material layer is formed, a via hole exposing the second pad of the substrate is formed in the injection molding material layer by means of laser drilling, and a metal layer is filled in the via hole by means of deposition or plating.
14. 14. The method of claim 10, wherein the first metal balls, the metal pillars, or the metal layer are made of copper or tin.
15. 15. The method of claim 10, wherein the second metal line is at least one of gold, silver, copper, or an alloy thereof.
16. 16. The method of packaging a semiconductor chip as claimed in claim 12, wherein the bonding is soldering.
17. 17. The packaging method of a semiconductor chip according to claim 8, wherein the third via includes a third metal line and/or a second metal ball, one end of which is connected to a pad of the image signal processing chip, and the other end of which is connected to the rewiring layer.
18. 18. The method of packaging a semiconductor chip as claimed in claim 17, wherein a third metal line is formed between the pad of the image signal processing chip and the first pad of the substrate by wire bonding before the injection molding material layer is formed, and the third metal line is cut and exposed by thinning the injection molding material layer after the injection molding material layer is formed.
19. 19. The method of packaging a semiconductor chip as claimed in claim 17, wherein the second metal balls are formed on the pads of the image signal processing chip by soldering before the injection molding material layer is formed, and the second metal balls are exposed by thinning the injection molding material layer after the injection molding material layer is formed.
20. 20. The method of packaging a semiconductor chip as claimed in claim 17, wherein a second metal ball is formed on a pad of the image signal processing chip by soldering before the injection molding material layer is formed, and a third metal wire is pulled out from the second metal ball and cut, and wherein the third metal wire is exposed by thinning the injection molding material layer after the injection molding material layer is formed.

Description

Packaging method and packaging structure of semiconductor chip Technical Field The invention relates to a packaging method and a packaging structure of a semiconductor chip. Background In the prior art, a semiconductor chip is generally packaged by a substrate, the semiconductor chip is disposed on the substrate, a pad of the semiconductor chip is electrically connected to the substrate, and the substrate is electrically connected to the outside. For example, an image signal processing chip (ISP chip) applied to a camera module of an electronic device is electrically connected with an external image sensor chip (CIS chip) assembly through a substrate, the CIS chip assembly is assisted in processing image information through the ISP chip, and processed data is transmitted to a terminal device through a connector. However, the substrate is used as a main component of the signal transmission path, and the wiring difficulty is high and the signal transmission speed and quality are easily affected under the limitation of limited area and layer number, so that a packaging method and a packaging structure with low wiring difficulty of the substrate are required to be designed, the auxiliary processing of image information by the CIS chip is realized, the module performance is improved, and the overall cost is reduced. Disclosure of Invention The invention aims to provide a packaging method and a packaging structure of a semiconductor chip, which reduce wiring difficulty, save packaging area, improve signal transmission speed and quality, improve performance of the packaging structure and reduce overall cost. In order to solve the technical problems, the invention provides a packaging method of a semiconductor chip, which comprises the steps of providing a substrate and at least one semiconductor chip arranged on the substrate, wherein a bonding pad of the semiconductor chip is electrically communicated with the substrate, the substrate is electrically communicated with the outside, and the bonding pad of the semiconductor chip is further provided with an upward connection structure so as to realize direct electrical communication of the semiconductor chip with the outside. Preferably, the structure of the upward connection of the semiconductor chip includes connection by a metal wire. Preferably, the electrical communication of the substrate with the outside comprises an upwardly connected structure and a downwardly connected structure, the upwardly connected structure of the substrate comprising a connection by a metal wire. Preferably, the semiconductor chip is an image signal processing chip, a pad of the image signal processing chip is connected to the substrate through a first via, the substrate is connected to one of an external image sensor chip assembly or connector through an upwardly connected second via and is connected to the other of the image sensor chip assembly or connector through a downwardly connected fourth via, and a pad of the image signal processing chip is also connected to one of the image sensor chip assembly or connector through an upwardly connected third via. Preferably, at least two semiconductor chips are stacked on the substrate, wherein each semiconductor chip is provided with an upward connection structure to enable the semiconductor chips to be directly electrically connected to the outside. Preferably, the at least two semiconductor chips include an image signal processing chip and a memory chip. Preferably, the substrate includes a first surface and a second surface opposite to each other, the image signal processing chip is fixed on the first surface of the substrate and covered with an injection molding material layer, a rewiring layer is disposed on the injection molding material layer, the rewiring layer is connected with one of the image sensor chip assembly or the connector, and the second surface of the substrate is connected with the other of the image sensor chip assembly or the connector. Preferably, the first via includes a first metal line, one end of which is connected to the first pad of the substrate, and the other end of which is connected to the pad of the image signal processing chip. Preferably, the routing direction of the first metal wire is from the first bonding pad of the substrate to the bonding pad of the image signal processing chip, so as to reduce the height of the first metal wire. Preferably, the second via includes a first metal ball, a metal pillar, a via hole filled with a metal layer, or a second metal line, one end of the first metal ball, the metal pillar, the via hole filled with the metal layer, or the second metal line is connected to the second pad of the substrate, and the other end is connected to the redistribution layer. Preferably, before forming the injection molding material layer, the two ends of the second metal wire are connected with the second bonding pad of the substrate in a wire bonding mode, and after forming the injectio