CN-122029497-A - Segmented clock gating

Abstract

The disclosed apparatus includes various circuit blocks and a clock tree for transmitting clock signals to the circuit blocks. The clock tree includes various clock drivers. The apparatus also includes a control circuit that power gates a portion of the clock tree including one of the clock drivers in response to one of the circuit blocks being power-gated. Various other methods, systems, and computer-readable media are also disclosed.

Inventors

• Benjamin Tsien
• Pravish Gupta
• Madu Sultan Chirakam
• Jeffrey Lynn Freeman
• Indrani Paul
• KRISHNAN GUHAN
• An M. Ling Ling
• Changdana Yemene

Assignees

• 超威半导体公司

Dates

Publication Date

20260512

Application Date

20240613

Priority Date

20231228

Claims (20)

1. 1. An apparatus, the apparatus comprising: A clock tree configured to transmit a clock signal to a plurality of circuit blocks; a clock driver for driving the clock tree, and A control circuit configured to power down the clock driver.
2. 2. The apparatus of claim 1, wherein a circuit block of the plurality of circuit blocks is power-gated, and the control circuit is further configured to power-up the clock driver to enable power-gating circuit blocks to be powered up.
3. 3. The device of claim 1, wherein the control circuit is configured to power up the clock driver in response to a wake-up event received by the control circuit.
4. 4. The apparatus of claim 3, wherein the wake event corresponds to a second circuit block interfacing with the circuit block.
5. 5. The apparatus of claim 3, wherein the wake event is part of a daisy chain of wake events from respective circuit blocks of the plurality of circuit blocks.
6. 6. The apparatus of claim 3, wherein the wake event corresponds to a temporary exit from powering down the clock driver.
7. 7. The apparatus of claim 6, wherein the temporary exit corresponds to a register access to the circuit block, and the control circuitry is further configured to: powering up the clock driver for the register access, and The clock driver is powered down in response to the register access being completed.
8. 8. The device of claim 3, wherein the wake-up event corresponds to a partial power state in which the circuit block is power-off and the clock driver is powered on while other circuit blocks remain power-on.
9. 9. A system, the system comprising: a plurality of segments, each segment comprising a circuit block; A plurality of clock drivers, each configured to drive a clock signal to a respective segment of the plurality of segments, and A control circuit configured to: Power gating segments of the plurality of segments, and Corresponding ones of the plurality of clock drivers associated with the power gating segment are powered down.
10. 10. The system of claim 9, further comprising a plurality of power gates for power gating the plurality of segments.
11. 11. The system of claim 9, wherein the hierarchy of the plurality of clock drivers corresponds to dependencies that drive the clock signals between clock drivers of the plurality of clock drivers.
12. 12. The system of claim 11, further comprising a clock generator corresponding to a root of the hierarchy of the plurality of clock drivers.
13. 13. The system of claim 11, wherein the hierarchy of the plurality of clock drivers corresponds to a sequence from most-gated clock drivers to least-gated clock drivers such that less-gated clock drivers are configured to drive the clock signal to more-gated clock drivers.
14. 14. The system of claim 13, wherein the control circuit is further configured to power down one or more of the plurality of clock drivers based on the sequence.
15. 15. The system of claim 13, wherein the control circuit is further configured to power on one or more of the plurality of clock drivers based on a sequence from the least-gated clock driver to the most-gated clock driver in response to a wake event, and to exit power gating of one or more of the plurality of segments based on the sequence from the least-gated clock driver to the most-gated clock driver in response to the wake event.
16. 16. The system of claim 9, wherein the control circuit is configured to: Receiving wake-up events targeting several of the plurality of segments, and The wake event is propagated asynchronously to the target segment.
17. 17. The system of claim 9, wherein the control circuit is configured to: powering up the clock driver in response to a wake-up event corresponding to a temporary exit; exiting power gating for the segment; Power gating the segment in response to the lapse of a temporary exit condition, and Powering down the clock driver.
18. 18. A method, the method comprising: In response to a power gating event, power gating one or more circuit blocks; powering down segmented clock drivers corresponding to the one or more circuit blocks; Powering up the clock driver in response to a wake-up event, and Power gating in the one or more circuit blocks is exited.
19. 19. The method of claim 18, wherein exiting power gating in the one or more circuit blocks further comprises waiting for a clock signal driven by the clock driver to resume before exiting power gating in the segment.
20. 20. The method of claim 18, wherein the wake event propagates asynchronously with respect to the one or more circuit blocks.

Description

Segmented clock gating Background As computing devices increase in complexity and performance requirements increase, power management becomes increasingly important to meet performance requirements. In addition, certain devices (such as mobile devices that run on batteries) may have additional limitations on power management. Power gating techniques may save power by shutting off the supply of power to a component or block of components. Clock gating techniques may also save power by removing clock signals from unused components. However, despite such techniques, the clock tree (e.g., a clock distribution network including clock circuitry for generating the clock signal and additional components for transmitting/modifying the clock signal to an appropriate destination) may still consume a significant amount of power. Drawings The accompanying drawings illustrate various exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure. FIG. 1 is a block diagram of an exemplary system of segmented clock gating (segment clock gating). Fig. 2A-2B are block diagrams of an exemplary clock tree and segment layout that may be segment clock-gated. FIG. 3 is a block diagram of an exemplary power delivery network for segmented clock gating. FIG. 4 is a flow chart of an exemplary method for segment clock gating. Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims. Detailed Description The present disclosure relates generally to segmented clock gating. As will be explained in more detail below, implementations of the present disclosure may perform segment clock gating by powering down clock drivers of a clock tree to stop clock propagation in segments of the clock tree downstream of the powered down clock drivers. The clock tree may be organized into a hierarchy of segments, with more powered segments being segment clock-gated after the relevant segments and re-powered in reverse order. By powering down the clock driver, additional power savings beyond power gating logic (e.g., combinational and/or sequential logic) and memory (e.g., on-die memory such as SRAM, DRAM, flash, and/or other memory arrays) in the segment may be achieved. In addition, powering down the clock driver based on the hierarchical structure of the segments and the corresponding sequence allows the clock driver to be powered up in a reverse sequence, which may be coordinated with powering up of logic and memory in the segments (e.g., by propagating a free running clock from the portion of the clock tree that remains powered up). In one implementation, an apparatus for segmented clock gating includes a clock tree configured to send a clock signal to a plurality of circuit blocks and a control circuit configured to power down a clock driver. In some examples, a circuit block of the plurality of circuit blocks is power-gated, and the control circuit is further configured to power-up the clock driver to enable the power-gated circuit block to be powered up. In some examples, the control circuit is further configured to power up the clock driver in response to a wake-up event received by the control circuit. In some examples, the wake event corresponds to a second circuit block interfacing with the circuit block. In some examples, the wake event is part of a daisy chain of wake events from several of the plurality of circuit blocks. In some examples, the wake event corresponds to a temporary exit from powering down the clock driver. In some examples, the temporary exit corresponds to a register access to the circuit block, and the control circuit is further configured to power down the clock driver in response to the register access being completed and the circuit block being power-gated. In some examples, the wake event corresponds to a partial power state. In some examples, the partial power state corresponds to the circuit block exiting power gating and the clock driver is powered on while the other circuit blocks remain power gated. In one implementation, a system for segment clock gating includes a plurality of segments each including a circuit block, a plurality of clock drivers each configured to drive a clock signal to a respective segment of the plurality of segments, and a control circuit configured to power gate a segment of the plura