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CN-122029509-A - Memory controller and memory system for handling power loss

CN122029509ACN 122029509 ACN122029509 ACN 122029509ACN-122029509-A

Abstract

In certain aspects, a memory system includes a non-volatile storage device and a memory controller coupled to the non-volatile storage device. The memory controller is configured to generate indicator data based on data to be initially programmed to the non-volatile storage and to control transmission of the indicator data to the non-volatile storage in response to a power loss of the memory system. The indicator data is configured to recover the source data.

Inventors

  • LIU WEILIN

Assignees

  • 长江存储科技有限责任公司

Dates

Publication Date
20260512
Application Date
20240910

Claims (20)

  1. 1. A storage system, comprising: Nonvolatile memory device A memory controller coupled to the non-volatile storage and configured to: Generating indicator data based on source data to be initially programmed to the non-volatile storage device, wherein the indicator data is configured to recover the source data, and The transmission of the indicator data to the non-volatile storage is controlled in response to a power loss of the storage system.
  2. 2. The storage system of claim 1 wherein the memory controller is further configured to control initial programming of the source data to the non-volatile storage such that the source data is intermediate data on the non-volatile storage.
  3. 3. The storage system of claim 2, wherein the memory controller is further configured to retrieve the intermediate data and the indicator data and recover the source data based on the intermediate data and the indicator data in response to a power recovery of the storage system.
  4. 4. The storage system of claim 2, wherein the non-volatile storage is configured to recover the source data based on the intermediate data and the indicator data and to send the recovered data to the memory controller in response to a power recovery of the storage system.
  5. 5. The storage system of any of claims 2-4, wherein the non-volatile storage is further configured to, after the initial programming of the source data, program the source data to make the source data programmed data.
  6. 6. The storage system of any of claims 1-5, wherein the indicator data comprises a bitmap.
  7. 7. The storage system of any of claims 1-6, wherein a size of the indicator data is smaller than a size of the source data.
  8. 8. The storage system of any of claims 1-7, wherein the memory controller comprises a volatile memory configured to store the indicator data.
  9. 9. The memory system of any of claims 1-8, further comprising a Power Loss Protection (PLP) circuit coupled to the memory controller and the non-volatile storage and configured to provide power to the memory controller and the non-volatile storage in response to the power loss of the memory system.
  10. 10. The storage system of any of claims 1-9, wherein the memory controller is configured to control the transmission of the indicator data to the non-volatile storage only in response to the power consumption of the storage system.
  11. 11. The memory system of any one of claims 1-10, wherein the non-volatile memory device comprises a NAND flash memory device.
  12. 12. A memory controller, comprising: An interface coupled to the non-volatile memory device, and A processor coupled to the interface and configured to: Generating indicator data based on source data to be initially programmed to the non-volatile storage device, wherein the indicator data is configured to recover the source data, and The transmission of the indicator data to the non-volatile storage is controlled through the interface in response to a power loss of the memory controller.
  13. 13. The memory controller of claim 12, wherein the processor is configured to control initial programming of the source data to the non-volatile storage via the interface such that the source data is intermediate data on the non-volatile storage.
  14. 14. The memory controller of claim 13, wherein, The interface is further configured to retrieve the intermediate data and the indicator data from the non-volatile storage in response to a power restoration of the memory controller, and The processor is further configured to recover the source data based on the intermediate data and the indicator data.
  15. 15. The memory controller of claim 13, wherein, The interface is further configured to receive the recovered data from the non-volatile storage device and The source data is restored by the non-volatile storage device based on the intermediate data and the indicator data in response to a power restoration of the memory controller.
  16. 16. The memory controller of any one of claims 13-15, wherein the processor is further configured to control programming of the source data to the non-volatile storage device such that the source data is programmed data on the non-volatile storage device after the initial programming of the source data.
  17. 17. The memory controller of any of claims 12-16, wherein the indicator data comprises a bitmap.
  18. 18. The memory controller of any of claims 12-17, wherein a size of the indicator data is smaller than a size of the source data.
  19. 19. The memory controller of any of claims 12-18, further comprising a volatile memory configured to store the indicator data.
  20. 20. The memory controller of any one of claims 12-19, wherein the processor is configured to control the transmission of the indicator data to the non-volatile storage only in response to the power consumption of the memory controller.

Description

Memory controller and memory system for handling power loss Technical Field The present disclosure relates to a memory device and a method of operating the same. Background Flash memory is a low cost, high density, non-volatile solid state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations such as reading, programming (writing) and erasing. For NAND flash memory, an erase operation may be performed at a block level, and a program operation or a read operation may be performed at a page level. Disclosure of Invention In one aspect, a memory system includes a non-volatile storage device and a memory controller coupled to the non-volatile storage device. The memory controller is configured to generate indicator data based on source data to be initially programmed to the non-volatile storage and to control transmission of the indicator data to the non-volatile storage in response to a power loss of the storage system. The indicator data is configured to recover the source data. In some implementations, the memory controller is further configured to control initial programming of the source data to the non-volatile storage such that the source data is intermediate data on the non-volatile storage. In some implementations, the memory controller is further configured to retrieve (retrieve) the intermediate data and the indicator data in response to a power restoration of the storage system, and restore the source data based on the intermediate data and the indicator data. In some implementations, the nonvolatile storage is configured to recover the source data based on the intermediate data and the indicator data in response to a power recovery of the storage system and send the recovered source data to the memory controller. In some implementations, the non-volatile storage is configured to program the source data to make the source data programmed after the initial programming of the source data. In some implementations, the indicator data includes a bitmap. In some implementations, the indicator data is smaller in size than the source data. In some implementations, the memory controller includes a volatile memory configured to store the indicator data. In some implementations, the memory system further includes a Power Loss Protection (PLP) circuit coupled to the memory controller and the non-volatile storage and configured to provide power to the memory controller and the non-volatile storage in response to the power loss of the memory system. In some implementations, the memory controller is configured to control transmission of the indicator data to the non-volatile storage only in response to the power consumption of the storage system. In some implementations, the non-volatile storage includes NAND flash storage. In another aspect, a memory controller includes an interface coupled to a non-volatile storage device and a processor coupled to the interface. The processor is configured to generate indicator data based on source data to be initially programmed to the non-volatile storage and to control transmission of the indicator data to the non-volatile storage through the interface responsive to a power loss of the memory controller. The indicator data is configured to recover the source data. In some implementations, the processor is configured to control initial programming of the source data to the non-volatile storage via the interface such that the source data is intermediate data on the non-volatile storage. In some implementations, the interface is further configured to retrieve the intermediate data and the indicator data from the non-volatile storage in response to a power restoration of the memory controller. In some implementations, the processor is further configured to recover the source data based on the intermediate data and the indicator data. In some implementations, the interface is further configured to receive the recovered data from the non-volatile storage. In some implementations, the source data is restored by the non-volatile storage device based on the intermediate data and the indicator data in response to a power restoration of the memory controller. In some implementations, the processor is further configured to control programming of the source data to the non-volatile storage device after the initial programming of the source data such that the source data is programmed data on the non-volatile storage device. In some implementations, the indicator data includes a bitmap. In some implementations, the indicator data is smaller in size than the source data. In some implementations, the memory controller further includes a volatile memory configured to store the indicator data. In some implementations, the processor is configured to control transmission of the indicator data to the non-volatile storage only in response to the power consumption of the memory cont