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CN-122029510-A - Multiplex bus sequential sequence management

CN122029510ACN 122029510 ACN122029510 ACN 122029510ACN-122029510-A

Abstract

A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select a first decoded memory access request for a first dummy channel from the command queue stage, and a second arbiter operable to select a second decoded memory access request for a second dummy channel from the command queue stage. Each of the first and second arbiters is operable to select a first contiguous sequence of accesses of a first type and to change to select a second contiguous sequence of accesses of a second type in response to the first and second arbiters meeting a cross mode condition.

Inventors

  • Kedarnat Barrisnan
  • James. R. Magro

Assignees

  • 超威半导体公司

Dates

Publication Date
20260512
Application Date
20241028
Priority Date
20240920

Claims (15)

  1. 1. A memory controller, comprising: A command queue stage for storing decoded memory access requests; a first arbiter operable to select a first decoded memory access request for a first pseudo channel from the command queue stage, and A second arbiter operable to select a second decoded memory access request for a second pseudo channel from the command queue stage, and Wherein each of the first arbiter and the second arbiter is operable to select a first consecutive sequence of accesses of a first type and to change to select a second consecutive sequence of accesses of a second type in response to the first arbiter and the second arbiter meeting a cross-mode condition.
  2. 2. The memory controller of claim 1, wherein: The first type of access comprising one of a read access and a write access, and The second type of access includes the other of the read access and the write access.
  3. 3. The memory controller of claim 1, wherein: The cross-mode condition is based on a total number of accesses of the second type for both the first pseudo-channel and the second pseudo-channel in the command queue stage.
  4. 4. The memory controller of claim 3, wherein: the cross-mode condition is further based on a history of the first type of access selected for both the first pseudo-channel and the second pseudo-channel in the command queue stage.
  5. 5. The memory controller of claim 1, wherein: the cross-mode condition is based on a total number of accesses of the second type for the respective dummy channel in the command queue stage and the second consecutive sequence that the other of the first arbiter and the second arbiter indicates that it is ready to switch to select the second type of access.
  6. 6. The memory controller of claim 5, further comprising: an address decoder having an upstream port for receiving memory access requests and a downstream port coupled to the command queue stage for providing the decoded memory access requests according to a pseudo-channel number, Wherein the address decoder further scrambles memory accesses between the first and second dummy channels based on one or more address bits of a normalized address.
  7. 7. The memory controller of claim 1, further comprising: A dispatch queue having first and second upstream ports and a downstream port, the first and second upstream ports coupled to the first and second arbiters, respectively, the downstream port is for conducting first data from the first arbiter that is time multiplexed with second data from the second arbiter.
  8. 8. A data processing system, comprising: A plurality of data processor cores, each of the plurality of data processor cores operable to generate a memory access request; A memory having a first dummy channel and a second dummy channel, and The memory controller of any one of claims 1 to 7.
  9. 9. The data processing system of claim 8, wherein the memory comprises a multiplexed column dual inline memory module (MRDIMM).
  10. 10. A method for accessing memory, comprising: Storing memory access requests in a command queue stage, wherein each memory access request accesses one of a first pseudo channel and a second pseudo channel of the memory; arbitrating among the memory access requests in an arbitration stage to obtain a first arbitration winner for the first pseudo channel using a first arbiter and to obtain a first arbitration winner for the second pseudo channel using a second arbiter; selecting a first sequential sequence of accesses of a first type by the first arbiter, and A second consecutive sequence of accesses of a second type is selected in response to the first arbiter and the second arbiter meeting a cross-mode condition.
  11. 11. The method according to claim 10, wherein: The first sequential sequence of the first type of access selected by the first arbiter includes the first sequential sequence of one of read access and write access, and The second consecutive sequence of changes to select the second type of access includes changes to the other of the read access and the write access.
  12. 12. The method according to claim 10, wherein: meeting the cross-mode condition includes meeting the cross-mode condition based on a total number of accesses of the second type for both the first pseudo-channel and the second pseudo-channel in the command queue stage.
  13. 13. The method according to claim 12, wherein: satisfying the cross-mode condition further includes satisfying the cross-mode condition based on a history of the first type of access in the command queue stage selected for both the first pseudo-channel and the second pseudo-channel.
  14. 14. The method according to claim 10, wherein: Meeting the cross-mode condition includes meeting the cross-mode condition based on a total number of accesses of the second type for a respective dummy channel in the command queue stage and the second consecutive sequence of accesses of the second type indicated by the other of the first arbiter and the second arbiter as being ready to switch to selection of the second type of access.
  15. 15. The method of claim 10, further comprising: Receiving a memory access request; Decoding an address of the memory access request to form a decoded memory access request, the decoding including scrambling the memory access between the first and second pseudo-channels based on one or more address bits of a normalized address, and The decoded memory access request is provided to the command queue stage according to a pseudo-channel number.

Description

Multiplex bus sequential sequence management Background Modern Dynamic Random Access Memory (DRAM) provides high memory bandwidth by increasing the data transfer speed on the bus connecting the DRAM and one or more data processors, such as Graphics Processing Units (GPUs), central Processing Units (CPUs), and the like. DRAM is typically inexpensive and high density, enabling each device to integrate a large number of DRAMs. Most DRAM chips sold today are compatible with the various Double Data Rate (DDR) DRAM standards promulgated by the joint electronic equipment engineering council (JEDEC). Typically, several DDR DRAM chips are combined onto a single printed circuit board substrate to form a memory module that can provide not only relatively high speed but also scalability. Higher processing speeds and storage capabilities are particularly useful in applications such as high-end servers for data centers, and new memory types that increase memory access speeds at reasonable cost and memory controllers that can take advantage of the features of the new memory types are desirable. The multiplexed column dual inline memory module (MRDIMM) is a new memory module form factor that can be used for very high speed and performance applications such as servers for data centers. Currently MRDIMM uses a conventional double data rate version 5 (DDR 5) memory device with dedicated Register Clock Driver (RCD) and Data Buffer (DB) chips while running a very fast memory bus interface between MRDIMM and the memory controller. MRDIMM have two independent channels (referred to as dummy channels) on the DIMM that are accessed over a shared high-speed memory bus between MRDIMM and the memory controller. While the dummy channels are mostly autonomous, these dummy channels need to perform the same type of memory access (i.e., read or write) at the same time to avoid contention on the bus, which makes it difficult to design a modular circuit for each dummy channel. Drawings FIG. 1 illustrates, in block diagram form, a data processing system having a memory system in accordance with some implementations; FIG. 2 illustrates, in block diagram form, a memory access architecture for use with MRDIMM of FIG. 1 in accordance with some implementations; Fig. 3 collectively illustrates a timing diagram useful in understanding the interface between the memory controllers and MRDIMM of fig. 1 and 2, according to some implementations, where fig. 3A is a first portion of the timing diagram showing a set of RCD signals sent between the physical interface circuit of fig. 1 and the memory on MRDIMM using the RCD of fig. 2, and fig. 3B is a second portion of the timing diagram showing a set of DB signals sent between the physical interface circuit of fig. 1 and the memory on MRDIMM using the DB of fig. 2; FIG. 4 illustrates, in block diagram form, a memory controller having MRDIMM virtual controller modes in accordance with some implementations; FIG. 5 illustrates a block diagram of a memory controller having MRDIMM virtual controller modes, according to other implementations; FIG. 6 illustrates a block diagram of an arbitration circuit that may be used with the memory controllers of FIGS. 4 and 5, according to some implementations; FIG. 7 illustrates a block diagram of another portion of a memory controller that may be used with the memory controllers of FIGS. 4 and 5, and in accordance with some implementations Fig. 8 illustrates a flow chart of a process that may be used for MRDIMM consecutive sequence management, according to some implementations. In the following description, the use of the same reference symbols in different drawings indicates similar or identical items. Unless otherwise indicated, the word "couple" and its associated verb forms include both direct connections and indirect electrical connections through means known in the art, and any description of a direct connection also means an alternative implementation using an appropriate form of indirect electrical connection, unless otherwise indicated. The following detailed description relates to electronic circuits, and unless indicated otherwise, the description of blocks shown in the drawings means that suitable electronic circuits are used to implement the described functions. Detailed Description The MRDIMM system supports a high-speed form factor that uses a common bus to communicate time multiplexed signals for two pseudo channels at extremely high bus speeds. The two dummy channels are mostly independent but are constrained by the need to operate in the same mode (read mode or write mode) at the same time to avoid bus contention. According to the disclosed implementations, existing memory controller arbitration circuitry may be modular and reused by ensuring that the arbitration circuitry for the dummy channel meets a cross-mode condition, where a cross-mode condition is a condition where the arbitration circuitry is ready to switch from a current mode (e.g., read or write)