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CN-122029513-A - Multi-format operand circuit

CN122029513ACN 122029513 ACN122029513 ACN 122029513ACN-122029513-A

Abstract

The disclosed processing circuit may perform an operation on a first operand having a first digital format and a second operand having a second digital format by directly using the first operand in the first digital format and the second operand in the second digital format to produce an output result. Various other methods, systems, and computer-readable media are also disclosed.

Inventors

  • Schuberger Shah
  • Ashutosh Gage
  • HE BIN
  • Michael Man Te
  • Shubula Ravi Marwaha
  • Subramaniam Meyulan

Assignees

  • 超威半导体公司

Dates

Publication Date
20260512
Application Date
20241018
Priority Date
20231228

Claims (15)

  1. 1. An apparatus, the apparatus comprising: Processing circuitry configured to perform an operation on a first operand having a first digital format and a second operand having a second digital format by directly using the first operand and the second operand to generate an output result.
  2. 2. The apparatus of claim 1, wherein the first digital format and the second digital format correspond to different ones of a plurality of digital formats having similar precision, and the processing circuitry is configured to perform the operation for each of a plurality of possible combinations of the plurality of digital formats of the first operand and the second operand.
  3. 3. The apparatus of claim 2, wherein the processing circuitry comprises circuitry to perform the operation for each of the plurality of possible combinations.
  4. 4. A device according to claim 2 or 3, wherein the processing circuitry comprises a set of instructions for performing the operation for each of the plurality of possible combinations.
  5. 5. The apparatus of claim 2,3 or 4, wherein the processing circuitry is further configured to decode the operation into a micro-operation using the first digital format and the second digital format.
  6. 6. The apparatus of claim 5, wherein the micro-operation comprises a micro-operation to normalize a first sign, a first exponent, and a first mantissa of the first operand based on the first digital format and to normalize a second sign, a second exponent, and a second mantissa of the second operand based on the second digital format.
  7. 7. The apparatus of claim 6, wherein the micro-operation comprises a micro-operation to combine the first and second symbols, the first and second mantissas, and the first and second exponents according to the operation to produce the output result.
  8. 8. The apparatus of any of claims 1 to 7, wherein the processing circuitry is further configured to perform the operation on a third operand having a third digital format by directly using the third operand in the third digital format to produce the output result.
  9. 9. The apparatus of claim 8, wherein the processing circuitry is configured to perform the operation on the first operand, the second operand, and the third operand by: performing a preliminary operation directly using the first operand in the first digital format and the second operand in the second digital format to produce an initial result, and A secondary operation is performed directly using the third operand in the third digital format and the initial result to produce the output result.
  10. 10. A system, the system comprising: Memory, and The processing circuitry is configured to process the data, the processing circuit is configured to: for an operation, receiving a first operand having a first digital format and a second operand having a second digital format from the memory; decoding the operation into a micro-operation using the first digital format and the second digital format, and The operations are performed via decoded micro-operations that directly use the first operand in the first digital format and the second operand in the second digital format to produce output results.
  11. 11. The system of claim 10, wherein the first digital format and the second digital format correspond to different digital formats of a plurality of digital formats having similar precision.
  12. 12. The system of claim 11, wherein the processing circuitry is configured to decode the operation into the micro-operation by selecting a micro-operation corresponding to one of a plurality of possible combinations of the plurality of digital formats of the first operand and the second operand.
  13. 13. The system of claim 12, wherein the processing circuit is further configured to select the micro-operation based on a first source of the first operand and a second source of the second operand.
  14. 14. The system of any of claims 10 to 13, wherein the micro-operation comprises a micro-operation for: normalizing a first sign, a first exponent, and a first mantissa of the first operand based on the first digital format; Normalizing a second sign, a second exponent, and a second mantissa of the second operand based on the second digital format, and The first sign and the second sign, the first mantissa and the second mantissa, and the first exponent and the second exponent are combined according to the operation to generate the output result.
  15. 15. The system of any of claims 10 to 14, wherein the processing circuitry is further configured to perform the operation on a third operand having a third digital format by directly using the third operand in the third digital format to produce the output result.

Description

Multi-format operand circuit Cross Reference to Related Applications The present application claims the benefit of U.S. provisional application No. 63/591,963 filed on day 10, month 20 of 2023 and U.S. patent application No. 18/399,659 filed on day 12, 2023, the disclosures of which are incorporated herein by reference in their entirety. Background Floating point numbers are commonly used by computing devices to represent a wide range of real values for computation. Different floating point number formats may be configured for various considerations, such as storage space/bandwidth considerations, computational considerations, mathematical properties, and the like. Furthermore, different computing devices may be configured to support different floating point number formats. As computing devices become more complex (e.g., have different types of hardware working in concert, use of networking devices, etc.) and computing demands increase (e.g., by implementing machine learning models, particularly for fast decision making), it may be desirable to support different floating point formats. While software-based support for different floating point formats is possible, software support typically results in increased latency or may not be feasible for particular application requirements. Drawings The accompanying drawings illustrate various exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure. FIG. 1 is a block diagram of an exemplary system of multi-format operand circuits. FIGS. 2A-2C are diagrams of an example floating point number format. FIG. 3 is a simplified block diagram of circuitry for a multi-format operand. FIG. 4 is a flow chart of an exemplary method of multi-format source operands. Throughout the drawings, identical reference numbers and descriptions indicate similar, but not necessarily identical elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims. Detailed Description The present disclosure relates generally to multi-format source operand circuits. As will be explained in more detail below, implementations of the present disclosure directly utilize a first operand having a first digital format and a second operand having a second digital format to perform operations. By producing output results without first converting either the first operand or the second operand to a digital format common to both, the systems and methods described herein increase computer processing efficiency and provide additional flexibility in performing computations on values from different sources (e.g., other processing components and/or devices). Additionally, the systems and methods provided herein may improve the field of machine learning by allowing improved decision-making and greater hardware compatibility by reducing the overhead for converting values into a shared number format while maintaining fast processing. In one implementation, an apparatus for multi-format operands includes a processing circuit configured to perform an operation on a first operand having a first digital format and a second operand having a second digital format by directly using the first operand and the second operand in the first digital format to produce an output result. In some examples, the first digital format and the second digital format correspond to different digital formats of a plurality of digital formats having similar precision. In some examples, the processing circuitry is configured to perform the operation for each of a plurality of possible combinations of a plurality of digital formats of the first operand and the second operand. In some examples, the processing circuitry includes circuitry to perform operations for each of a plurality of possible combinations. In some examples, the processing circuitry includes a set of instructions for performing operations for each of a plurality of possible combinations. In some examples, the processing circuitry is further configured to decode the operation into a micro-operation using the first digital format and the second digital format. In some examples, the micro-operation includes a micro-operation to normalize a first sign, a first exponent, and a first mantissa of a first operand based on a first digital format and to normalize a second sign, a second exponent, and a second mantissa of a second operand based on a second digital format. In some examples, the micro-opera