CN-122029524-A - LPDDR5 DRAM WCK clock power saving through command buffering

Abstract

Methods, systems (200), and media include a memory controller configured to control writing to a memory, wherein the memory controller is configured to issue a fixed write to the memory with or without enabling a data clock, wherein the memory controller is configured to perform operations including receiving a write command including a regular write command and a fixed write command, bulk processing (202, wrx=1) the fixed write command until one or more fixed write bulk processing criteria are met, disabling the data clock, and issuing a batch including a plurality of fixed writes corresponding to the fixed write command.

Inventors

• ANANTHANARAYANAN VENKATASUBRAM

Assignees

• 谷歌有限责任公司

Dates

Publication Date

20260512

Application Date

20231017

Claims (20)

1. 1. A memory controller configured to control writing to a memory, wherein the memory controller is configured to issue a fixed write to the memory with or without enabling a data clock, Wherein the memory controller is configured to perform operations comprising: Receiving a write command including a normal write command and a fixed write command; batch processing the fixed write commands until one or more fixed write batch processing criteria are met; disabling the data clock, and A batch is issued that includes a plurality of fixed writes corresponding to the fixed write commands.
2. 2. The memory controller of claim 1, wherein the operations further comprise determining that the one or more fixed write batch processing criteria are met comprises determining that at least a threshold number of fixed write commands have been received since a last batch of fixed writes was issued.
3. 3. The memory controller of any one of claims 1 to 2, wherein the operations further comprise determining that the one or more fixed write batch processing criteria are met comprises determining that at least a threshold period of time has elapsed since a last batch of fixed writes was issued.
4. 4. The memory controller of any one of claims 1 to 3, wherein the operations further comprise determining that the one or more fixed write batch processing criteria are met comprises determining that at least a threshold number of total write commands have been received since a last batch of fixed writes was issued.
5. 5. The memory controller of any one of claims 1 to 4, wherein each fixed write command represents a command to write a consecutive all 1 or all 0 sequence.
6. 6. The memory controller of any one of claims 1 to 5, further comprising fixed write batch processing standard logic configured to receive a sequence of write commands and provide a request to issue a batch of fixed writes to a write scheduler each time the one or more fixed write batch processing standards are met.
7. 7. The memory controller of any one of claims 1 to 6, wherein disabling the data clock disables clock flipping at a data pin of the memory.
8. 8. A method of controlling writing to a memory, comprising: Receiving a write command comprising a regular write command and a fixed write command at a memory controller configured to control writing to a memory, wherein the memory controller is configured to issue a fixed write to the memory with or without enabling a data clock; batch processing the fixed write commands until one or more fixed write batch processing criteria are met; disabling the data clock, and A batch is issued that includes a plurality of fixed writes corresponding to the fixed write commands.
9. 9. The method of claim 8, further comprising determining that the one or more fixed write batch processing criteria are met comprises determining that at least a threshold number of fixed write commands have been received since a last batch of fixed writes was issued.
10. 10. The method of any one of claims 8 to 9, further comprising determining that the one or more fixed write batch processing criteria are met, including determining that at least a threshold period of time has elapsed since a last batch of fixed writes was issued.
11. 11. The method of any one of claims 8 to 10, further comprising determining that the one or more fixed write batch processing criteria are met, including determining that at least a threshold number of total write commands have been received since a last batch of fixed writes was issued.
12. 12. The method of any of claims 8 to 11, wherein each fixed write command represents a command to write a consecutive all 1 or all 0 sequence.
13. 13. The method of any of claims 8 to 12, further comprising receiving a sequence of write commands and providing a request to issue a batch of fixed writes to the write scheduler each time one or more fixed write batch processing criteria are met.
14. 14. The method of any of claims 8 to 13, wherein disabling the data clock disables clock flipping at a data pin of the memory.
15. 15. One or more storage media encoded with instructions that, when executed by a data processing apparatus, cause the data processing apparatus to perform operations comprising: Receiving a write command comprising a regular write command and a fixed write command at a memory controller configured to control writing to a memory, wherein the memory controller is configured to issue a fixed write to the memory with or without enabling a data clock; batch processing the fixed write commands until one or more fixed write batch processing criteria are met; disabling the data clock, and A batch is issued that includes a plurality of fixed writes corresponding to the fixed write commands.
16. 16. The one or more storage media of claim 15, wherein the operations further comprise determining that the one or more fixed write batch processing criteria are met comprise determining that at least a threshold number of fixed write commands have been received since a last batch of fixed writes was issued.
17. 17. The one or more storage media of any of claims 15 to 16, wherein the operations further comprise determining that the one or more fixed write batch processing criteria are met comprise determining that at least a threshold period of time has elapsed since a last batch of fixed writes was issued.
18. 18. The one or more storage media of any of claims 15 to 17, wherein the operations further comprise determining that the one or more fixed write batch processing criteria are met comprise determining that at least a threshold number of total write commands have been received since a last batch of fixed writes was issued.
19. 19. The one or more storage media of any of claims 15 to 18, wherein each fixed write command represents a command to write a consecutive all 1 or all 0 sequence.
20. 20. The one or more storage media of any of claims 15 to 19, wherein the operations further comprise receiving a sequence of write commands and providing a request to issue a batch of fixed writes to a write scheduler each time one or more fixed write batch processing criteria are met.

Description

LPDDR5 DRAM WCK clock power saving through command buffering Background The present specification relates to a technique for saving energy when writing a Dynamic Random Access Memory (DRAM). Writing to random access memory is an important source of power consumption for battery powered devices such as mobile phones and tablet computers. Accordingly, various techniques have been developed to reduce the amount of power consumed by writing to DRAM. As one example, the LPDDR5 protocol specifies a type of write command (e.g., WRX command) that does not require power-hungry toggling of the data clock. However, because normal write commands and special write commands are not sent in a particular order, DRAM systems such as LPDDR5 do not consistently utilize the ability to stop the data clock when writing special write commands. This may result in unnecessary power consumption, which may be considerable due to the higher clock frequency of the data clock. Such data clocks typically operate at a much faster rate than the system command clock, e.g., two or four times faster. Disclosure of Invention The present specification relates to a power saving technique that buffers certain classes of write commands issued to a random access memory to save power. One such example DRAM is a Low Power Double Data Rate (LPDDR) Dynamic Random Access Memory (DRAM), e.g., an LPDDR5 DRAM. Whereas WRX commands (e.g., a "fixed data" write command) do not require a data clock ("WCK clock") to write, buffering conventional and fixed data write commands may be advantageous to minimize the operation of the WCK clock in order to save power. In some cases, such as in the joint electronics engineering council (JEDEC) specification, there is a minimum amount of time required between write commands that must be met in order to turn off the WCK clock. When write commands are sent in a non-specific order, this time requirement may prevent the WCK clock from being turned off for WRX commands that do not require the WCK clock, as the minimum time between write commands is not always met. By controlling how write commands are written, these minimum time requirements can be met without impeding the advantages of stopping the WCK clock. For example, the WCK clock may be turned off to execute these fixed commands by buffering fixed data writes until a specified amount is accumulated. By turning off the WCK clock to execute these fixed write commands, power savings are achieved because the WCK clock may be power intensive to operate based on its higher clock frequency. For example, when a device starts an application, a large number of fixed write commands may be generated. The WCK clock writes commands when they are received without controlling how regular and fixed write commands are executed. An example of this process is provided in prior art fig. 1, which will be discussed in detail later. As shown in fig. 1, the WCK clock receives regular and fixed write commands in a non-specific order. Thus, the WCK clock continuously toggles as it executes the write command. In contrast, FIG. 3 illustrates an example process for batch processing fixed write commands. As shown in FIG. 3, the WCK may be shut down to write the fixed write command by batch processing the fixed write command until the conventional write command has been written. This results in less clock operation and achieves device power savings when compared to fig. 1. Although examples of application launch are described above, there are other examples when a large number of fixed write commands are generated. For example, a large number of fixed write commands may be generated in response to a particular input stimulus that produces a predominantly fixed data value (e.g., all "1" or "0"). In these examples, the WCK may also be turned off using the techniques of this specification to achieve device power savings. Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages. Advantages may include device power savings by shutting down the WCK clock to execute a fixed write command. Since the WCK clock operates at a high frequency (e.g., twice or four times faster than the command clock), significant device power savings can be achieved even if the WCK clock is only briefly turned off. The device energy conservation achieved by the technology of the present specification can extend the battery life of the host device, reduce the device power consumption and heat generation, and reduce the device operating cost. The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. Drawings FIG. 1 is an overview of an example prior art method of writing commands in a DRAM. FIG. 2 is an example system