CN-122029525-A - Radio frequency interference common mode injection in a C-PHY receiver

Abstract

An input buffer (800) includes a pair of input transistors (802 a,802 b) and associated injection circuitry (806, 808). The first input transistor (802 a) has a source (824 a) coupled to a first voltage rail (832) through a first current source (812) and a gate coupled to a first conductor (810) of a multi-wire serial bus. Three or more resistors in the first injection circuit (806) couple the wires of the serial bus (832) to a first common node (822 a) coupled by a first capacitor to the source (824 a) of the first input transistor (802 a). The second input transistor (802 b) has a source (824 b) coupled to the first voltage rail (832) through a second current source (814) and a gate coupled to a second conductor (820) of the serial bus. Three or more resistors in the second injection circuit (808) couple the wires (832) of the multi-wire serial bus to a second common node (822 b) coupled by a second capacitor to the source (824 b) of the second input transistor (802 b).

Inventors

• P. Devasha Shivarama
• DUAN YING
• CAO QINQING
• S.SUN
• M. B. Sheikh
• A. Dixit

Assignees

• 高通股份有限公司

Dates

Publication Date

20260512

Application Date

20240822

Priority Date

20230906

Claims (20)

1. 1. An input buffer, the input buffer comprising: a first input transistor having a source coupled to a first voltage rail through a first current source and a gate coupled to a first conductor of a multi-wire serial bus; a first injection circuit, the first injection circuit comprising: Three or more resistors configured to couple wires of the multi-wire serial bus to a common node of the first injection circuit, and A capacitor configured to couple the common node of the first injection circuit to the source of the first input transistor; A second input transistor having a source coupled to the first voltage rail through a second current source and a gate coupled to a second conductor of the multi-wire serial bus, and A second injection circuit, the second injection circuit comprising: three or more resistors configured to couple wires of the multi-wire serial bus to a common node of the second injection circuit, and A capacitor configured to couple the common node of the second injection circuit to the source of the second input transistor.
2. 2. The input buffer of claim 1, wherein the multi-wire serial bus comprises a three-wire serial bus operating in accordance with a Mobile Industry Processor Interface (MIPI) alliance C-PHY protocol.
3. 3. The input buffer of claim 2, wherein the first injection circuit comprises three resistors, and wherein the first injection circuit is associated with a termination impedance that is at least five times greater than a characteristic impedance of the three-wire serial bus.
4. 4. The input buffer of claim 1, the input buffer further comprising: a source degeneration circuit configured to couple the source of the first input transistor with the source of the second input transistor.
5. 5. The input buffer of claim 4, wherein the source degeneration circuit comprises a programmable resistor-capacitor network.
6. 6. The input buffer of claim 1, wherein a drain of the first input transistor is coupled to a second voltage rail through a first output resistor and a drain of the second input transistor is coupled to the second voltage rail through a second output resistor.
7. 7. The input buffer of claim 6, wherein the input buffer is provided in a first stage of a differential receiver circuit, and wherein the drains of the first and second input transistors are coupled to an input of a second stage of the differential receiver circuit.
8. 8. The input buffer of claim 6, the input buffer further comprising: a source degeneration circuit coupling the source of the first input transistor with the source of the second input transistor, Wherein the source degeneration circuit is configured to control a common mode voltage measured between the drains of the first and second input transistors.
9. 9. The input buffer of claim 1, wherein the first injection circuit and the second injection circuit are configured to pass signals generated in a three-wire serial bus by radio frequency interference and block signals encoded according to MIPI alliance C-PHY protocol.
10. 10. The input buffer of claim 1, wherein the input buffer is provided in a first differential receiver circuit, and wherein each combination of two wires in a three-wire serial bus is coupled to one of three differential receiver circuits.
11. 11. A method for buffering signals received from a multi-wire serial bus, the method comprising: receiving a first signal at a gate of a first input transistor via a first conductor of a multi-wire serial bus, the first input transistor having a source coupled to a first voltage rail by a first current source; Receiving a second signal at a gate of a second input transistor via a second conductor of the multi-wire serial bus, the second input transistor having a source coupled to the first voltage rail by a second current source, and Common mode noise is injected into the sources of the first and second input transistors using: A first injection circuit having a capacitor and three or more resistors, each wire of the multi-wire serial bus being coupled to a first common node through the three or more resistors of the first injection circuit and the first common node being coupled to the source of the first input transistor through the capacitor of the first injection circuit, and A second injection circuit having a capacitor and three or more resistors, each wire of the multi-wire serial bus coupled to a second common node through the three or more resistors of the second injection circuit, and the second common node coupled to the source of the second input transistor through the capacitor of the second injection circuit.
12. 12. The method of claim 11, wherein the multi-wire serial bus comprises a three-wire serial bus operating in accordance with a Mobile Industry Processor Interface (MIPI) alliance C-PHY protocol.
13. 13. The method of claim 12, wherein the first injection circuit comprises three resistors, and wherein the first injection circuit is associated with a termination impedance that is at least five times as large as a characteristic impedance of the three-wire serial bus.
14. 14. The method of claim 11, wherein a source degeneration circuit is configured to couple the source of the first input transistor with the source of the second input transistor.
15. 15. The method of claim 14, wherein the source degeneration circuit comprises a programmable resistor-capacitor network.
16. 16. The method of claim 14, the method further comprising: The source degeneration circuit is configured to control a common mode voltage measured between drains of the first input transistor and the second input transistor.
17. 17. The method of claim 11, wherein a drain of the first input transistor is coupled to a second voltage rail through a first output resistor and a drain of the second input transistor is coupled to the second voltage rail through a second output resistor.
18. 18. The method of claim 17, wherein the first input transistor and the second input transistor are provided in a first stage of a differential receiver circuit, and wherein drains of the first input transistor and the second input transistor are coupled to an input of a second stage of the differential receiver circuit.
19. 19. The method of claim 11, wherein the first injection circuit and the second injection circuit are configured to pass signals generated in a three-wire serial bus by radio frequency interference and block signals encoded according to MIPI alliance C-PHY protocol.
20. 20. The method of claim 11, wherein each combination of two wires in a three-wire serial bus is coupled to one of three differential receiver circuits.

Description

Radio frequency interference common mode injection in a C-PHY receiver Cross Reference to Related Applications This patent application claims priority from pending U.S. non-provisional application serial No. 18/462,107, filed on 6, 9, 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated by reference as if fully set forth below and for all applicable purposes. Technical Field The present disclosure relates generally to serial communications via a serial bus in a wireless communication device, and more particularly to common mode radio frequency interference in a C-PHY interface. Background Mobile communication devices typically include various components such as circuit boards, integrated Circuit (IC) devices, application Specific Integrated Circuit (ASIC) devices, and/or system on a chip (SoC) devices. The types of components may include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to a standardized protocol or a proprietary protocol. In one example, the serial bus may operate according to an inter-integrated circuit (I2C or I2C) communication protocol. The I2C bus is configured as a multi-drop bus and is developed to connect low-speed peripherals to the processor. The two conductors of the I2C bus include a serial data line (SDA) carrying a data signal and a Serial Clock Line (SCL) carrying a clock signal. A number of standards are defined for interconnecting certain types of components in mobile communication devices. For example, different types of interfaces may be used for communication between an application processor and a display or camera component in a mobile communication device. Some displays or camera components employ interfaces that conform to standards or protocols specified by the Mobile Industry Processor Interface (MIPI) alliance for Camera Serial Interfaces (CSI) and Display Serial Interfaces (DSI). The MIPI alliance DSI, DSI-2 (referred to herein individually or collectively as DSI), and CSI-2 (referred to herein individually or collectively as CSI) standards define a wired interface that may be deployed within an IC or between some combination of an IC device and an SoC device. The CSI protocol may be used to couple the camera and the application processor. The DSI protocol may be used to couple an application processor and a display subsystem. The low-level physical layer (PHY) interface in each of these applications may be implemented according to MIPI alliance C-PHY or D-PHY standards and protocols. A high speed mode and a low power mode of communication are defined for the C-PHY interface and the D-PHY interface. The C-PHY high speed mode uses low voltage multi-phase signals sent in different phases over a 3-wire link. The D-PHY high speed mode uses multiple 2-wire lanes to carry low voltage differential signals. The low power modes of the C-PHY interface and the D-PHY interface provide lower rates and transmit signals at higher voltages than the high speed modes. The application processor and associated camera and display subsystem may be subject to electromagnetic interference (EMI) from a variety of sources, including co-located Radio Frequency (RF) transceivers, including RF transmitter circuitry and antennas. As device technology improves, the combination of higher data rate demands on the serial bus has been met in some cases by increasing the clock rate used to control signaling on the serial interface. For example, the release 2.0 specification for the MIPI C-PHY interface provides a transmit clock rate between 4.5GHz and 6.0 GHz. Increasing the transmit clock frequency may reduce the tolerance and margin defined for the data signal and may exacerbate the effects of EMI. For these and other reasons, there is a continuing need for improved EMI suppression capabilities of high speed interfaces. Disclosure of Invention Certain aspects of the present disclosure relate to systems, devices, methods, and techniques that may improve common mode noise suppression at a receiver coupled to a C-PHY three-wire communication link. In various aspects of the present disclosure, an input buffer includes a pair of input transistors and associated injection circuitry. The first input transistor has a source coupled to the first voltage rail through a first current source and a gate coupled to a first conductor of the multi-wire serial bus. The first injection circuit includes three or more resistors configured to couple the conductor of the multi-wire serial bus to a common node of the first injection circuit. The first injection circuit further includes a capacitor configured to couple the common node of the first injection circuit to the source of the first input transistor. A second input transistor has a source coupled to the first voltage rail through a second current source and a gate coupled to a second conductor