CN-122029526-A - Memory device and processor having processing circuitry

Abstract

Memory devices and processors having processing circuitry are disclosed. An apparatus may include a first memory device, a second memory device, and a computing device. The first memory device can include a first base die and a first memory die attached to the first base die. The first base die may include a first die-to-die interface, a second die-to-die interface, and a first processing circuit. The second memory device can include a second base die and a second memory die attached to the second base die. The second base die may include a third die-to-die interface, a fourth die-to-die interface, and a second processing circuit. The computing device may be connected to a first die-to-die interface and a third die-to-die interface.

Inventors

• Rika Pichumani
• DING XUANQUAN
• JIANG LIANGXU
• Qi Liangshi
• Zheng Xiuji
• ZHENG MINGJUN

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250517

Priority Date

20250516

Claims (20)

1. 1. An apparatus, comprising: a first memory device comprising a first base die and a first memory die, the first base die comprising a first die-to-die interface, a second die-to-die interface, and a first processing circuit, the first memory die attached to the first base die; A second memory device including a second base die and a second memory die, the second base die including a third die-to-die interface, a fourth die-to-die interface, and a second processing circuit, the second memory die attached to the second base die, and A computing device is connected to the first die-to-die interface and the third die-to-die interface.
2. 2. The apparatus of claim 1, further comprising a network device connected to the second die-to-die interface.
3. 3. The apparatus of claim 2, wherein the network device is configured to interface with an accelerator link.
4. 4. The apparatus of claim 2, wherein the network device is configured to interface with a memory controller.
5. 5. The apparatus of claim 4, wherein the memory controller comprises a low power double data rate memory controller.
6. 6. The apparatus of claim 2, wherein the network device is connected to the computing device.
7. 7. The apparatus of claim 2, wherein the network device is connected to a fourth die-to-die interface.
8. 8. An apparatus, comprising: a first system in package, comprising: A first memory device including a first base die and a first memory die, the first base die including first processing circuitry and a first die-to-die interface, the first memory die attached to the first base die, and A first computing device connected to the first die-to-die interface; A second system in package, comprising: A second memory device including a second base die and a second memory die, the second base die including a second processing circuit and a second die-to-die interface, the second memory die attached to the second die-to-die interface, and A second computing device connected to the second die-to-die interface, and A first processor connected to the first system in package and the second system in package.
9. 9. The apparatus of claim 8, wherein the first system in package is connected to the second system in package by an accelerator link.
10. 10. The apparatus of claim 8, further comprising a first interface configured to connect the first system in package to a third system in package, the third system in package being connected to the second processor.
11. 11. The apparatus of claim 10, further comprising a second interface configured to connect the first processor to a network.
12. 12. The apparatus of claim 11, wherein the first interface is connected to the second interface.
13. 13. The system of claim 8, wherein the first base die includes a third die-to-die interface connected to the network device.
14. 14. The system of claim 13, wherein the network device is configured to interface with a low power double data rate memory controller.
15. 15. A system, comprising: A first tray, comprising: A first system in package comprising a first memory device comprising a first base die and a first memory die, the first base die comprising first processing circuitry, the first memory die attached to the first base die, and a first computing device connected to the first memory device, A second system in package comprising a second memory device and a second computing device, the second memory device comprising a second base die and a second memory die, the second base die comprising a second processing circuit, the second memory die attached to the second base die, the second computing device connected to the second memory device, and A first interface, and A second tray, comprising: A third system in package comprising a third memory device and a third computing device, the third memory device comprising a third base die and a third memory die, the third base die comprising third processing circuitry, the third memory die attached to the third base die, the third computing device connected to the third memory device, and And a second interface connected to the first interface.
16. 16. The system of claim 15, wherein a first system in package is connected to the first interface and a third system in package is connected to the second interface.
17. 17. The system of claim 15, wherein the first tray comprises a processor coupled to the first system in package and the second system in package.
18. 18. The system of claim 15, wherein the first tray includes a third interface configured to connect the processor to a network.
19. 19. The system of claim 18, wherein the first interface is connected to the third interface.
20. 20. The system of claim 15, wherein the first system in package is connected to the second system in package by an accelerator link.

Description

Memory device and processor having processing circuitry Data of related applications The present application claims the benefit of U.S. provisional patent application No. 63/649,012, filed 5/17/2024, which is incorporated herein by reference for all purposes. Technical Field The disclosure relates generally to memory devices and processors, and more particularly to memory devices and processors having processing circuitry. Background Computing resources and memory resources are utilized differently for different applications. Computing resources are typically provided by a processor (e.g., a central processing unit), while memory resources are typically provided by memory (e.g., random access memory). The performance of the application and operations within the application may be limited based on computing resources, memory resources, or both. Drawings The drawings described below are examples of how the disclosed embodiments may be implemented and are not intended to limit the disclosed embodiments. Various embodiments disclosed may include elements not shown in a particular drawing and/or may omit elements shown in a particular drawing. The drawings are intended to provide an illustration and may not be to scale. FIG. 1 illustrates a system including a memory device and a computing device in accordance with a disclosed embodiment. Fig. 2 illustrates a memory die of a memory device according to a disclosed embodiment. Fig. 3 illustrates a base die of a memory device according to a disclosed embodiment. Fig. 4 illustrates a processing circuit according to a disclosed embodiment. Fig. 5 illustrates an example of a system in package according to a disclosed embodiment. Fig. 6 illustrates an example of a system in package according to a disclosed embodiment. Fig. 7 illustrates an example of a system in package according to a disclosed embodiment. Fig. 8 illustrates a computing/memory tray in accordance with a disclosed embodiment. Disclosure of Invention An apparatus may include a first memory device, a second memory device, and a computing device. The first memory device can include a first base die and a first memory die attached to the first base die. The first base die may include a first die-to-die interface, a second die-to-die interface, and a first processing circuit. The second memory device can include a second base die and a second memory die attached to the second base die. The second base die may include a third die-to-die interface, a fourth die-to-die interface, and a second processing circuit. The computing device may be connected to a first die-to-die interface and a third die-to-die interface. An apparatus may include a first system-in-package, a second system-in-package, and a first processor connected to the first system-in-package and the second system-in-package. The first system in package may include a first memory device and a first computing device. The first memory device may include a first base die and a first memory die attached to the first base die, the first base die including first processing circuitry and a first die-to-die interface. The first computing device may be connected to a first die-to-die interface. The second system in package may include a second memory device and a second computing device. The second memory device may include a second base die and a second memory die attached to the second base die, the second base die including second processing circuitry and a second die-to-die interface. The second computing device may be connected to a second die-to-die interface. A system may include a first tray and a second tray. The first tray may include a first system in package, a second system in package, and a first interface. The first system-in-package may include a first memory device and a first computing device connected to the first memory device. The first memory device may include a first base die and a first memory die attached to the first base die, the first base die including first processing circuitry. The second system in package may include a second memory device and a second computing device connected to the second memory device. The second memory device may include a second base die and a second memory die attached to the second base die, the second base die including second processing circuitry. The second tray may include a third system in package and a second interface. The third system in package may include a third memory device and a third computing device connected to the third memory device. The third memory device may include a third base die and a third memory die attached to the third base die, the third base die including third processing circuitry. The second interface may be connected to the first interface. Detailed Description Reference will now be made in detail to the disclosed embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth