CN-122029527-A - Memory device with processing circuit

Abstract

Memory devices having processing circuits are disclosed. An apparatus may include a first memory device and a second memory device. The first memory device can include a first base die and a first memory die attached to the first base die. The first base die may include a first processing circuit, a second processing circuit, and a first die-to-die interface. The second memory device can include a second base die and a second memory die attached to the second base die. The second base die may include a third processing circuit and a second die-to-die interface. The first memory device may be configured to communicate with the second memory device using the first die-to-die interface and the second die-to-die interface.

Inventors

• Rika Pichumani
• DING XUANQUAN
• JIANG LIANGXU
• Qi Liangshi
• Zheng Xiuji
• ZHENG MINGJUN

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250517

Priority Date

20250516

Claims (20)

1. 1. An apparatus, comprising: A first memory device including a first base die and a first memory die, the first base die including first processing circuitry, second processing circuitry, and a first die-to-die interface, the first memory die attached to the first base die, and A second memory device including a second base die and a second memory die, the second base die including third processing circuitry and a second die-to-die interface, the second memory die attached to the second base die, Wherein the first memory device is configured to communicate with the second memory device using the first die-to-die interface and the second die-to-die interface.
2. 2. The apparatus of claim 1, wherein the first processing circuit comprises a first memory and a first processor, and the second processing circuit comprises a second memory and a second processor.
3. 3. The apparatus of claim 2, wherein the first processing circuit is connected to the second processing circuit and a portion of the second memory is accessible to the first processing circuit.
4. 4. The apparatus of claim 1, wherein the first die-to-die interface is connected to the second die-to-die interface.
5. 5. The apparatus of claim 1, further comprising a network device connected to a third die-to-die interface included in the first base die.
6. 6. The apparatus of claim 1, wherein the first base die comprises a network on chip configured to interface with a memory controller.
7. 7. The apparatus of claim 1, wherein the first base die comprises a network on chip configured to interface with an accelerator link.
8. 8. An apparatus, comprising: A first memory device including a first base die and a first memory die, the first base die including a first processing circuit, a first die-to-die interface, and a second die-to-die interface, the second die-to-die interface being connected to the network device, the first memory die being attached to the first base die, and A second memory device including a second base die and a second memory die, the second base die including second processing circuitry, third processing circuitry, a third die-to-die interface, a fourth die-to-die interface, the third processing circuitry being connected to the second processing circuitry, the third die-to-die interface being connected to the first die-to-die interface, the second memory die being attached to the second base die.
9. 9. The apparatus of claim 8, wherein the network device is configured to interface with the memory.
10. 10. The apparatus of claim 9, wherein the memory comprises a low power double data rate LPDDR memory.
11. 11. The apparatus of claim 8, further comprising a low power double data rate LPDDR memory controller connected to the fourth die-to-die interface.
12. 12. The apparatus of claim 11, wherein the LPDDR memory controller is connected to the first die-to-die interface.
13. 13. The apparatus of claim 8, wherein the second processing circuit comprises a first processor and a first memory, and the third processing circuit comprises a second processor and a second memory.
14. 14. The apparatus of claim 13, wherein the second memory is accessible by the second processing circuit and the third processing circuit.
15. 15. An apparatus, comprising: a first set of memory devices comprising: a first memory device including a first base die and a first memory die, the first base die including first processing circuitry, the first memory die being attached to the first base die, and A second memory device connected to the first memory device, the second memory device including a second base die and a second memory die, the second base die including second processing circuitry, the second memory die being attached to the second base die; A second set of memory devices comprising: A third memory device including a third base die and a third memory die, the third base die including third processing circuitry, the third memory die being attached to the third base die, and A fourth memory device connected to the third memory device, the fourth memory device including a fourth base die and a fourth memory die, the fourth base die including fourth processing circuitry, the fourth memory die attached to the fourth base die, and And a controller connected to the first set of memory devices and the second set of memory devices.
16. 16. The apparatus of claim 15, wherein the controller comprises a first die-to-die interface connected to the network device.
17. 17. The apparatus of claim 16, wherein the network device is configured to interface with a memory controller.
18. 18. The apparatus of claim 16, wherein the network device is configured to interface with an accelerator link.
19. 19. The apparatus of claim 15, further comprising a memory coupled to the controller.
20. 20. The apparatus of claim 19, wherein the first portion of memory is accessible by a first set of memory devices and the second portion of memory is accessible by a second set of memory devices.

Description

Memory device with processing circuit Data of related applications The present application claims the benefit of U.S. provisional patent application No. 63/649,012, filed 5/17/2024, which is incorporated herein by reference for all purposes. Technical Field The disclosure relates generally to memory devices and, more particularly, to memory devices having processing circuitry. Background Computing resources and memory resources are utilized differently for different applications. Computing resources are typically provided by a processor (e.g., a central processing unit), while memory resources are typically provided by memory (e.g., random access memory). The performance of the application and operations within the application may be limited based on computing resources, memory resources, or both. Drawings The drawings described below are examples of how the disclosed embodiments may be implemented and are not intended to limit the disclosed embodiments. Various embodiments disclosed may include elements not shown in a particular drawing and/or may omit elements shown in a particular drawing. The drawings are intended to provide an illustration and may not be to scale. FIG. 1 illustrates a system including a memory device according to a disclosed embodiment. Fig. 2 illustrates a memory die of a memory device according to a disclosed embodiment. Fig. 3 illustrates a base die of a memory device according to a disclosed embodiment. Fig. 4 illustrates a processing circuit according to a disclosed embodiment. Fig. 5 illustrates an example of a system in package according to a disclosed embodiment. Fig. 6 illustrates an example of a system in package according to a disclosed embodiment. Fig. 7 illustrates an example of a system in package according to a disclosed embodiment. Fig. 8 illustrates a computing/memory tray in accordance with a disclosed embodiment. Disclosure of Invention An apparatus may include a first memory device and a second memory device. The first memory device can include a first base die and a first memory die attached to the first base die. The first base die may include a first processing circuit, a second processing circuit, and a first die-to-die interface. The second memory device can include a second base die and a second memory die attached to the second base die. The second base die may include a third processing circuit and a second die-to-die interface. The first memory device may be configured to communicate with the second memory device using the first die-to-die interface and the second die-to-die interface. An apparatus may include a first memory device and a second memory device. The first memory device can include a first base die and a first memory die attached to the first base die. The first base die may include a first processing circuit, a first die-to-die interface, and a second die-to-die interface connected to the network device. The second memory device can include a second base die and a second memory die attached to the second base die. The second base die may include a second processing circuit, a third processing circuit connected to the second processing circuit, a third die-to-die interface connected to the first die-to-die interface, and a fourth die-to-die interface. An apparatus may include a first set of memory devices, a second set of memory devices, and a controller connected to the first set of memory devices and the second set of memory devices. The first set of memory devices may include a first memory device and a second memory device connected to the first memory device. The first memory device may include a first base die and a first memory die attached to the first base die, the first base die including first processing circuitry. The second memory device may include a second base die and a second memory die attached to the second base die, the second base die including second processing circuitry. The second set of memory devices may include a third memory device and a fourth memory device connected to the third memory device. The third memory device may include a third base die and a third memory die attached to the third base die, the third base die including third processing circuitry. The fourth memory device may include a fourth base die and a fourth memory die attached to the fourth base die, the fourth base die including fourth processing circuitry. An apparatus may include a base die and a memory die attached to the base die. The memory die may include a first memory. The base die may include a first die-to-die interface, a second die-to-die interface, and processing circuitry. The processing circuit may include a processor, a second memory, and a cache. The first die-to-die interface may be configured to interface with a network device. The network device may include at least one of an input/output chiplet and a memory expansion chiplet. An apparatus may include a first memory device and a second memory device. The first memory device can